Address Configuration

This section covers the following topics:

• Address space overview.
• PCI address space.
• CPU address space.

Address Space Overview

The EV5 address space is divided into two regions using physical address bit [39]. If clear, then CPU access is to the cached memory space. If set, then the accesses are not cached. The uncached space is used to access memory-mapped I/O devices. Mailboxes are not supported. The uncached space contains the CSRs, uncached memory access (for diagnostics), and the PCI address space. The PCI defines three physical address spaces:

1. 64-bit PCI memory space.
2. 4-GB PCI I/O space.
3. 256-byte per device PCI configuration space.

In addition to the three PCI address spaces, the CPU's uncached space also generates PCI Interrupt Acknowledge and Special Cycles.

The system is capable of two modes of addressing: byte/word disabled (0) and byte/word enabled (1).. The mode is controlled by bit 0 (IOA_BEN) of the PYXIS_CTRL1 CSR.

Physical Address Map with Byte/Word Mode Disabled

Physical Address Map with Byte/Word Mode Enabled

The CPU has visibility to the complete address space: it can access cached memory, CSRs as well as all the PCI memory, I/O, and configuration regions. See Figure 3-1.

The PCI devices have a restricted view of the address space. Tthey can access any PCI device through the PCI memory or PCI I/O space, but they have no access to the PCI configuration space. Furthermore, the system restricts access to the system memory (for DMA operations) through five, programmable "windows" (i.e., memory regions) in the PCI memory space. (See figure below.)

DMA access to the system memory is achieved through "windows" in one of three ways:

1. Directly using the Monster Window with Dual Address Cycles where PCI address <33:0> equals memory address <33:0>.
2. Directly mapped by concatenating an offset to a portion of the PCI address.
3. Virtually through a scatter/gather translation map.

The scatter/gather map allows any 8-KB PCI memory address region (page) to be redirected to any 8-KB cached memory page, as shown below.

PCI address Space

The system generates 32-bit PCI addresses but accepts both 64-bit address (DAC, double address cycle) cycles and 32-bit PCI address (SAC, single address cycle) cycles. Main memory accessing is done as outlined below:

• Window [4], the Monster Window, gives full access to main memory. It is accessed by DAC only with PCI address<40> set. Memory address<33:0> equals PCI address <33:0>.
• Window [3] can be either DAC or SAC, but not both. If it is DAC, PCI address <63:40> must be zero, PCI address <39:32> must match the DAC register, and PCI address <31:0> must hit in Window [3].
• Window [2:0] are SAC only.

When the system is initialized by the SROM code, the windows are configured as follows:

CPU Address Space

The following figure shows an overview of the mapping of the 40-bit processor physical address space into memory and I/O space addresses:

     39      34 33 32 31
+---+---+---+--+--+--+--+------------------------------+
|   |   |SBZ|  |  |  |  |                              |
+---+---+---+--+--+--+--+------------------------------+
      /\- - - - - - - - - +--------+
      |      0   0  x  x  |        |  8-GB Cached
      |                   +--------+      Memory
      |                   |        |
 <39>=0= Cached           |Reserved|
      |  Memory           |        |
      |  Space            |        |
      |                   |        |
      |                   |        |
      \/                  |        |
      - - - - - - - - - - +--------+ - - - - - - 
      /\     0   x  x  x  |        | 80.0000.0000   /\
      |                   |        |                 |
      |                   | 16GB   |                 |
      |                   |        |            PCI Memory
      |                   |        |            Sparse Space
      |                   |        |            704-MB Max
      |                   +--------+                 |
      |      1   0  0  x  |  4-GB   | 84.0000.0000    |
 <39>=1= Uncached         |        |                 |
      |  I/O Space        +--------+                 |
      |      1   0  1  0  |  2-GB   | 85.0000.0000   \/
      |                   +--------+ - - - - - - -- - -
      |      1   0  1  1  |        | 85.8000.0000 PCI Sparse
      |                   |        |              I/O 64-MB
      |                   +--------+
      |      1   1  0  x  |        | 86.0000.0000 PCI Dense
      |                   |        |              Memory 4-GB
      |                   +--------+
      \/     1   1  1  x  |        | 87.0000.0000 PCI Config
      - - - - - - - - - - +--------+              CSRs, and
                                                    flashROM