Table 353. VGA Video Modes
========================================================================================
Mode |Type |Colors |Alpha |Buffer |Box |Max. |Freq |Resolution |Double |Border
(Hex) | | |Format |Start |Size |Pages | |(hxv Pixels) |Scan |Support
======|=====|=======|=======|========|=====|======|=====|=============|========|========
0,1 |A/N |16 |40x25 |B8000 |8x8 |8 |70Hz |320x200 |Yes |No
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
0*,1* |A/N |16 |40x25 |B8000 |8x14 |8 |70Hz |320x350 |No |No
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
0+,1+ |A/N |16 |40x25 |B8000 |9x16 |8 |70Hz |360x400 |No |No
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
2,3 |A/N |16 |80x25 |B8000 |8x8 |8 |70Hz |640x200 |Yes |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
2-,3- |A/N |16 |80x25 |B8000 |8x14 |8 |70Hz |640x350 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
2+,3+ |A/N |16 |80x25 |B8000 |9x16 |8 |70Hz |720x400 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
4,5 |APA |4 |40x25 |B8000 |8x8 |1 |70Hz |320x200 |Yes |No
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
6 |APA |2 |80x25 |B8000 |8x8 |1 |70Hz |640x200 |Yes |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
7 |A/N |- |80x25 |B0000 |9x14 |8 |70Hz |720x350 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
7+ |A/N |- |80x25 |B0000 |9x16 |8 |70Hz |720x400 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
D |APA |16 |40x25 |A0000 |8x8 |8 |70Hz |320x200 |Yes |No
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
E |APA |16 |80x25 |A0000 |8x8 |4 |70Hz |640x200 |Yes |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
F |APA |- |80x25 |A0000 |8x14 |2 |70Hz |640x350 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
10 |APA |16 |80x25 |A0000 |8x14 |2 |70Hz |640x350 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
11 |APA |2 |80x30 |A0000 |8x16 |1 |60Hz |640x480 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
12 |APA |16 |80x30 |A0000 |8x16 |1 |60Hz |640x480 |No |Yes
------|-----|-------|-------|--------|-----|------|-----|-------------|--------|--------
13 |APA |256 |40x25 |A0000 |8x8 |1 |70Hz |320x200 |Yes |Yes
========================================================================================
Note: * or + indicate enhanced modes
========================================================================================
Mode 3+ is the default mode with a color display attached and mode 7 is the default mode with a monochrome display attached. The graphics controller senses whether the display is monochrome or color and initializes itself to the appropriate mode.----------------------------- | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ----------------------------- | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -----------------------------
Figure 12. Character/Attribute Format
Table 354. Attribute Byte Definitions ========================================================== Bit |Color |Function ====|======|============================================== 7 | B/I |Blinking or Background Intensity ----|------|---------------------------------------------- 6 | R |Background Color ----|------|---------------------------------------------- 5 | G |Background Color ----|------|---------------------------------------------- 4 | B |Background Color ----|------|---------------------------------------------- 3 | I/CS |Foreground Intensity or Character Font Select ----|------|---------------------------------------------- 2 | R |Foreground Color ----|------|---------------------------------------------- 1 | G |Foreground Color ----|------|---------------------------------------------- 0 | B |Foreground Color ==========================================================The following are the color values loaded for the 16-color modes.
Table 355. Firmware Color Initialization
=============================
IRGB |Color
=====|=======================
0000 |Black
-----|-----------------------
0001 |Blue
-----|-----------------------
0010 |Green
-----|-----------------------
0011 |Cyan
-----|-----------------------
0100 |Red
-----|-----------------------
0101 |Magenta
-----|-----------------------
0110 |Brown
-----|-----------------------
0111 |White
-----|-----------------------
1000 |Gray
-----|-----------------------
1001 |Light Blue
-----|-----------------------
1010 |Light Green
-----|-----------------------
1011 |Light Cyan
-----|-----------------------
1100 |Light Red
-----|-----------------------
1101 |Light Magenta
-----|-----------------------
1110 |Yellow
-----|-----------------------
1111 |White (High Intensity)
|
=============================
Both 40-column and 80-column alphanumeric modes are supported. The features of the 40-column alphanumeric modes (all variations of modes 0 and 1) are:
The following figure shows the format for each byte.
Table 356. PEL Format, Modes 4 and 5
==============================
Bit |Function
====|=========================
7 | C1- First Display PEL
----|-------------------------
6 | C0 - First Display PEL
----|-------------------------
5 | C1- Second Display PEL
----|-------------------------
4 | C0 - Second Display PEL
----|-------------------------
3 | C1 - Third Display PEL
----|-------------------------
2 | C0 - Third Display PEL
----|-------------------------
1 | C1- Fourth Display PEL
----|-------------------------
0 | C0 - Fourth Display PEL
|
==============================
A maximum of 200 rows of 640 pels
Double scanned to display as 400 rows
Same addressing and scan-line mapping as 320 x 200 graphics
16,000 bytes of read/write memory.
Table 357. PEL Format, mode 6
=========================
Bit |Function
====|====================
7 |First Display PEL
----|--------------------
6 |Second Display PEL
----|--------------------
5 |Third Display PEL
----|--------------------
4 |Forth Display PEL
----|--------------------
3 |Fifth Display PEL
----|--------------------
2 |Sixth Display PEL
----|--------------------
1 |Seventh Display PEL
----|--------------------
0 |Eighth Display PEL
|
=========================
Table 358. Bit Definitions C2,C0
=========================
C2 C0 |PEL Color
======|==================
0 0 |Black
------|------------------
01 |White
------|------------------
1 0 |Blinking White
------|------------------
1 1 |Intensified White
|
=========================
Memory is organized with successive bytes defining successive pels. The first eight pels displayed are defined by the byte at 0xA0000, the second eight pels at 0xA0001, and so on. The most significant bit in each byte defines the first PEL for that byte.The following figure shows the color information that is compatible with the colors in other modes:
Table 359. Compatible Color Coding
=================================
PEL Bits |Color Output
76543210 |
=========|=======================
00000000 |Black
---------|-----------------------
00000001 |Blue
---------|-----------------------
00000010 |Green
---------|-----------------------
00000011 |Cyan
---------|-----------------------
00000100 |Red
---------|-----------------------
00000101 |Magenta
---------|-----------------------
00000110 |Brown
---------|-----------------------
00000111 |White
---------|-----------------------
00001000 |Gray
---------|-----------------------
00001001 |Light Blue
---------|-----------------------
00001010 |Light Green
---------|-----------------------
00001011 |Light Cyan
---------|-----------------------
00001100 |Light Red
---------|-----------------------
00001101 |Light Magenta
---------|-----------------------
00001110 |Yellow
---------|-----------------------
00001111 |White (High Intensity)
|
=================================
Each color in the palette can be programmed to one of 256K different colors.The features of this mode are:
A maximum of 200 rows with 320 pels
Double scanned to display as 400 rows
256 of 256K colors for each PEL
The question mark in the address can be a hex B or D depending on the setting of the I/O address bit in the Miscellaneous Output register, described in "General Registers" on page 203.
Table 360. VGA Subsystem Register Overview:
=============================================
Registers |R/W |Port
| |Address
===============================|====|========
General Registers | |
-------------------------------|----|--------
Sequencer Registers | |
Address Register |R/W |0x03C4
Data Registers |R/W |0x03C5
-------------------------------|----|--------
CRT Controller Registers | |
Address Register |R/W |0x03?4
Data Registers |R/W |0x03?5
-------------------------------|----|--------
Graphics Controller Registers | |
Address Register |R/W |0x03CE
Data Registers |R/W |0x03CF
-------------------------------|----|--------
Attribute Controller Registers | |
Address Register |R/W |0x03C0
Data Registers |W |0x03C0
|R |0x03C1
-------------------------------|----|--------
Video DAC Palette Registers | |
Write Address |R/W |0x03C8
Read Address |W |0x03C7
Data |R/W |0x03C9
PEL Mask |R/W |0x03C6
| |
=============================================
Table 361. General Registers:
==================================================
Register |Read |Write
|Address |Address
================================|========|========
Miscellaneous Output Register |0x03CC |0x03C2
--------------------------------|--------|--------
Input Status Register 0 |0x03C2 | -
--------------------------------|--------|--------
Input Status Register 1 |0x03?A | -
--------------------------------|--------|--------
Feature Control Register |0x03CA |0x03?A
--------------------------------|--------|--------
Video Subsystem Enable Register |0x03C3 |0x03C3
==================================================
================================
7 |6 |5 |4 |3 |2 |1 |0
----|----|--|--|--|--|-----|----
VSP |HSP |- |- |CS |ERAM |IOS
| | | | | |
================================
Miscellaneous Output Register
=====================================
- |: |Set to 0, undefined on Read
-----|--|----------------------------
VSP |: |Vertical Sync Polarity
-----|--|----------------------------
HSP |: |Horizontal Sync Polarity
-----|--|----------------------------
PB |: |Page Bit for Odd/Even
-----|--|----------------------------
CS |: |Clock Select
-----|--|----------------------------
ERAM |: |Enable RAM
-----|--|----------------------------
IOS |: |I/O Address Select
| |
=====================================
The register fields are defined as follows:
=============================================================================================================
VSP |Determines the polarity of the vertical sync pulse and can be used (with HSP) to control the vertical
|size of the display by utilizing the autosynchronization feature of VGA displays.
| = 0 selects a positive vertical retrace sync pulse.
|
=====|=======================================================================================================
HSP |Determines the polarity of the horizontal sync pulse.
| = 0 selects a positive horizontal retrace sync pulse.
|Bits 7 (VSP) and 6 (HSP) select the vertical size as follows:
| Bits
| 7 6 Vertical Size
| 0 0 - Reserved
| 0 1 - 400 lines
| 1 0 - 350 lines
| 1 1 - 480 lines
|
-----|-------------------------------------------------------------------------------------------------------
PB |Selects the upper/lower 64K page of memory when the system is in an eve/odd mode (modes
|0,1,2,3,7).
| = 0 selects the low page
| = 1 selects the high page
|
-----|-------------------------------------------------------------------------------------------------------
CS |These two bits select the clock source as below: The external clock is driven through the auxiliary
|video extension. The input clock should be kept between 14.3 MHz and 28.4 MHz.
| Bits
| 3 2 Function
| 0 0 - Selects 25 MHz clock for 640/320 Horizontal pels
| 0 1 - Selects 28 MHz clock for 720/360 Horizontal pels
| 1 0 - Reserved
| 1 1 - Reserved
|
-----|-------------------------------------------------------------------------------------------------------
ERAM |Controls system access to the display buffer.
| = 0 disables address decode for the display buffer from the system
| = 1 enables address decode for the display buffer from the system
|
-----|-------------------------------------------------------------------------------------------------------
IOS |This bit selects the CRT controller addresses. When set to 0, this bit sets the CRT controller ad-
|dresses to 0x03Bx and the address for the Input Status Register 1 to 0x03BA for compatibility with
|the monochrome adapter.
|When set to 1, this bit sets CRT controller addresses to 0x03Dx and the Input Status Register 1 ad-
|dress to 0x03DA for compatibility with the color/graphics adapter.
|The Write addresses to the Feature Control register are affected in the same manner.
|
=============================================================================================================
========================= 7 |6 |5 |4 |3 |2 |1 |0 ---|--|--|---|--|--|--|-- CI |- |- |SS |- |- |- |- | | | | | | | =========================
Input Status Register 0 =================================== - |: |Set to 0, undefined on Read ===|==|============================ CI |: |CRT Interrupt ---|--|---------------------------- SS |: |Switch Sense | | ===================================
The register fields are defined as follows: =========================================================================================================== CI |When set to 1, this bit indicates a vertical retrace interrupt is pending | ===|======================================================================================================= SS |Returns the status of the four sense switches as selected by the CS field of the Miscellaneous Output |Register. ===========================================================================================================
========================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|---|--|--|--- - |- |- |- |VR |- |- |DE | | | | | | | =========================
Input Status Register =================================== - |: |Set to 0, undefined on Read ===|==|============================ VR |: |Vertical Retrace ---|--|---------------------------- DE |: |Display Enable | | ===================================
The register fields are defined as follows: ================================================================================================================ VR |When set to 1, this bit indicates that the display is in a vertical retrace interval.This bit can be pro- |grammed, through the Vertical Retrace End register, to generate an interrupt at the start of the verti- |cal retrace. | ===|============================================================================================================ DE |When set to 1, this bit indicates a horizontal or vertical retrace interval. This bit is the real-time sta- |tus of the inverted 'display enable' signal. Programs have used this status bit to restrict screen up- |dates to the inactive display intervals in order to reduce screen flicker. The video subsystem is |designed to eliminate this software requirement; screen updates may be made at any time without |screen degradation. | ================================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Feature Control =======================
=======================
7 |6 |5 |4 |3 |2 |1 |0
--|--|--|--|--|--|--|--
Video Subsystem Enable
=======================
Table 362. Sequencer Registers
=============================
Register |Index
|(hex)
=====================|=======
Sequencer Address |-
---------------------|-------
Reset |00
---------------------|-------
Clocking Mode |01
---------------------|-------
Map Mask |02
---------------------|-------
Character Map Select |03
---------------------|-------
Memory Mode |04
=============================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |- |- |- |- |SA | | | | | =======================
Sequencer Address Register =================================== - |: |Set to 0, undefined on Read ===|==|============================ SA |: |Sequencer Address | | ===================================
The register field is defined as follows: ========================================================================================= SA | These bits contain the index value that points to the data register to be accessed. =========================================================================================
========================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|---|---- - |- |- |- |- |- |SR |ASR | | | | | | | ==========================
Reset Register
====================================
- |: |Set to 0, undefined on Read
====|==|============================
SR |: |Synchronous Reset
----|--|----------------------------
ASR |: |Asynchronous Reset
| |
====================================
The register fields are defined as follows:
=============================================================================================================
SR |When set to 0, this bit commands the sequencer to synchronously clear and halt. Bits 1 and 0 must
|be 1 to allow the sequencer to operate. To prevent the loss of data, bit 1 must be set to 0 during the
|active display interval before changing the clock selection. The clock is changed through the Clock-
|ing Mode register or the Miscellaneous Output register.
|
====|========================================================================================================
ASR |When set to 0, this bit commands the sequencer to asynchronously clear and halt. Resetting the se-
|quencer with this bit can cause loss of video data.
|
=============================================================================================================
============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|---|----|---|---|--|---- - |- |SO |SH4 |DC |SL |1 |D89 | | | | | | | ==============================
Clocking Mode Register
====================================
- |: |Set to 0, undefined on Read
----|--|----------------------------
1 |: |Set to 1, undefined on Read
====|==|============================
SO |: |Screen Off
----|--|----------------------------
SH4 |: |Shift 4
----|--|----------------------------
DC |: |Dot Clock
----|--|----------------------------
SL |: |Shift Load
----|--|----------------------------
D89 |: |8/9 Dot Clocks
| |
====================================
The register fields are defined as follows:
===============================================================================================================
SO |When set to 1, this bit turns off the display and assigns maximum memory bandwidth to the system.
|Although the display is blanked, the synchronization pulses are maintained. This bit can be used for
|rapid full-screen updates.
|
====|==========================================================================================================
SH4 |When the Shift 4 field and the Shift Load Field are set to 0, the video serializers are loaded every
|character clock. When the Shift 4 field is set to 1, the video serializers are loaded every forth charac-
|ter clock, which is useful when 32 bits are fetched per cycle and chained together in the shift regis-
|ters.
|
----|----------------------------------------------------------------------------------------------------------
DC |When set to 0, this bit selects the normal dot clocks derived from the sequencer master clock input.
|When this bit is set to 1, the master clock will be divided by 2 to generate the dot clock. All other
|timings are affected because they are derived from the dot clock. The dot clock divided by 2 is used
|for 320 and 360 horizontal PEL modes.
|
----|----------------------------------------------------------------------------------------------------------
SL |When this bit and bit 4 are set to 0, the video serializers are loaded every character clock. When this
|bit is set to 1, the video serializers are loaded every other character clock, which is useful when 16
|bits are fetched per cycle and chained together in the shift registers. The Type 2 video behaves as if
|this bit is set to 0; therefore, programs should set it to 0.
|
----|----------------------------------------------------------------------------------------------------------
D89 |When set to 0, this bit directs the sequencer to generate character clocks 9 dots wide; when set to 1,
|it directs the sequencer to generate character clocks 8 dots wide. The 9-dot mode is for alphanumeric
|modes 0+, 1+, 2+, 3+, 7, and 7 + only; the 9th dot equals the 8th dot for ASCII codes 0xC0 through
|0xDF. All other modes must use 8 dots per character clock. See the line graphics character bit in the
|"Attribute Mode Control Register" on page 228
|
===============================================================================================================
=============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|----|----|----|---- - |- |- |- |M3E |M2E |M1E |M0E | | | | | | | ===============================
Map Mask Register, Index 0x02
====================================
- |: |Set to 0, undefined on Read
====|==|============================
M3E |: |Map 3 Enable
----|--|----------------------------
M2E |: |Map 2 Enable
----|--|----------------------------
M1E |: |Map 1 Enable
----|--|----------------------------
M0E |: |Map 0 Enable
----|--|----------------------------
D89 |: |8/9 Dot Clocks
| |
====================================
The register fields are defined as follows:
=============================================================================================================
M*E |When set to 1, these bits enable system access to the corresponding map. If all maps are enabled, the
|system can write its 8-bit value to all four maps in a single memory cycle. This substantially reduces
|the system overhead during display updates in graphics modes.
|Data scrolling operations can be enhanced by enabling all maps and writing the display buffer ad-
|dress with the data stored in the system data latches. This is a Read-Modify-Write operation.
|When odd/even modes are selected, maps 0 and 1 and maps 2 and 3 should have the same map mask
|value.
|When chain 4 mode is selected, all maps should be enabled.
|
=============================================================================================================
1. Set the extended memory bit in the Memory Mode register (0x04) to 1.
2. Select different values for character map A and character map B.
This function is supported by BIOS and is a function call within the character generator routines.
=========================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|----|----|--|--|--|-- - |- |MAH |MBH |MAL |MBL | | | | | ===========================
Character Map Select Register, Index 0x03
=====================================
- |: |Set to 0, undefined on Read
====|==|=============================
MAH |: |Character Map A Select (MSB)
----|--|-----------------------------
MBH |: |Character Map B Select (MSB)
----|--|-----------------------------
MAL |: |Character Map A Select (LSB)
----|--|-----------------------------
MBL |: |Character Map B Select (LSB)
| |
=====================================
The register fields are defined as follows:
==============================================================================================================
MAH |This bit is the most-significant bit for selecting the location of character map A.
|
----|---------------------------------------------------------------------------------------------------------
MBH |This bit is the most-significant bit for selecting the location of character map B.
|
----|---------------------------------------------------------------------------------------------------------
MAL |These bits and bit 5 select the location of character map A. Map A is the area of map 2 containing
|the character font table used to generate characters when attribute bit 3 is set to 1. The selection is
|shown in Table 363 on page 209.
|
----|---------------------------------------------------------------------------------------------------------
MBL |These bits and bit 4 select the location of character map B. Map B is the area of map 2 containing the
|character font table used to generate characters when attribute bit 3 is set to 0. The selection is
|shown in Table 364 on page 209.
|
==============================================================================================================
Table 363. Character Map Select A
===========================================
Bits |Map |Table Location
532 |Selected |
=====|=========|===========================
000 |0 |1st 8KB of display memory
| |plane 2
-----|---------|---------------------------
001 |1 |3rd 8KB
-----|---------|---------------------------
010 |2 |5th 8KB
-----|---------|---------------------------
011 |3 |7th 8KB
-----|---------|---------------------------
100 |4 |2nd 8KB
-----|---------|---------------------------
101 |5 |4th 8KB
-----|---------|---------------------------
110 |6 |6th 8KB
-----|---------|---------------------------
111 |7 |8th 8KB
| |
===========================================
Table 364. Character Map Select B
===========================================
Bits |Map |Table Location
410 |Selected |
=====|=========|===========================
000 |0 |1st 8KB of display memory
| |plane 2
-----|---------|---------------------------
001 |1 |3rd 8KB
-----|---------|---------------------------
010 |2 |5th 8KB
-----|---------|---------------------------
011 |3 |7th 8KB
-----|---------|---------------------------
100 |4 |2nd 8KB
-----|---------|---------------------------
101 |5 |4th 8KB
-----|---------|---------------------------
110 |6 |6th 8KB
-----|---------|---------------------------
111 |7 |8th 8KB
| |
===========================================
=========================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|----|---|---|-- - |- |- |- |CH4 |OE |EM |- | | | | | | | ===========================
Memory Mode Register, Index 0x04
====================================
- |: |Set to 0, undefined on Read
====|==|============================
CH4 |: |Chain 4
----|--|----------------------------
OE |: |Odd/Even
----|--|----------------------------
EM |: |Extended Memory
| |
====================================
The register fields are defined as follows:
============================================================================================================
CH4 |This bit controls the map selected during system read operations. When set to 0, this bit enables sys-
|tem addresses to sequentially access data within a bit map by using the Map Mask register. When set
|to 1, this bit causes the two low-order bits to select the map accessed as shown below.
|
|Address Bits
| A0 A1 Map Selected
| 0 0 0
| 0 1 1
| 1 0 2
| 1 1 3
|
----|-------------------------------------------------------------------------------------------------------
OE |When this bit is set to 0, even system addresses access maps 0 and 2, while odd system addresses ac-
|cess maps 1 and 3. When this bit is set to 1, system addresses sequentially access data within a bit
|map, and the maps are accessed according to the value in the Map Mask register (index 0x02).
|
----|-------------------------------------------------------------------------------------------------------
EM |When set to 1, this bit enables the video memory from 64KB to 256KB. This bit must be set to 1 to
|enable the character map selection described for the previous register.
|
|
============================================================================================================
Table 365. CRT Controller Registers =============================================== Register Name |Address |Index ===============================|========|====== Address |0x03?4 |- -------------------------------|--------|------ Horizontal Total |0x03?5 |0x0 -------------------------------|--------|------ Horizontal Display-Enable End |0x03?5 |0x01 -------------------------------|--------|------ Start Horizontal Blanking |0x03?5 |0x02 -------------------------------|--------|------ End Horizontal Blanking |0x03?5 |0x03 -------------------------------|--------|------ Start Horizontal Retrace Pulse |0x03?5 |0x04 -------------------------------|--------|------ End Horizontal Retrace |0x03?5 |0x05 -------------------------------|--------|------ Vertical Total |0x03?5 |0x06 -------------------------------|--------|------ Overflow |0x03?5 |0x07 -------------------------------|--------|------ Preset Row Scan |0x03?5 |0x08 -------------------------------|--------|------ Maximum Scan Line |0x03?5 |0x09 -------------------------------|--------|------ Cursor Start |0x03?5 |0x0A -------------------------------|--------|------ Cursor End |0x03?5 |0x0B -------------------------------|--------|------ Start Address High |0x03?5 |0x0C -------------------------------|--------|------ Start Address Low |0x03?5 |0x0D -------------------------------|--------|------ Cursor Location High |0x03?5 |0x0E -------------------------------|--------|------ Cursor Location Low |0x03?5 |0x0F -------------------------------|--------|------ Vertical Retrace Start |0x03?5 |0x10 -------------------------------|--------|------ Vertical Retrace End |0x03?5 |0x11 -------------------------------|--------|------ Vertical Display-Enable End |0x03?5 |0x12 -------------------------------|--------|------ Offset |0x03?5 |0x13 -------------------------------|--------|------ Underline Location |0x03?5 |0x14 -------------------------------|--------|------ Start Vertical Blanking |0x03?5 |0x15 -------------------------------|--------|------ End Vertical Blanking |0x03?5 |0x16 -------------------------------|--------|------ CRT Mode Control |0x03?5 |0x17 -------------------------------|--------|------ Line Compare |0x03?5 |0x18 =============================================== Index values not listed are reserved. ===============================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |- |- |Index | | | =======================
Address Register
==============================================================================
- | |Set to 0, undefined on Read
------|--|--------------------------------------------------------------------
Index |: |These bits are the index that points to the data register accessed
| |through address 0x03D5 or 0x03B5.
==============================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Horizontal Total =======================This register the total number of characters in the horizontal scan interval including the retrace time. The value directly controls the period of the 'horizontal retrace' signal. A horizontal character counter in the CRT controller counts the character clock inputs; comparators are used to compare the register value with the character's horizontal width to provide horizontal timings. All horizontal and vertical timings are based on this register.
The value contained in this register is the total number of characters minus 5.
============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|--------- Horizontal Display Enable End ==============================The value in this register defines the length of the 'horizontal display-enable' signal, and determines the number of character positions per horizontal line. The value contained in this register is the total number of displayed characters minus 1.
========================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|----- Start Horizontal Blanking ==========================The value in this register is the horizontal character count where the 'horizontal blanking' signal goes active.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- 1 |DES |EB | | =======================
End Horizontal Blanking Register, Index 0x03
====================================
1 |: |Set to 1, undefined on Read
====|==|============================
DES |: |Display Enable Skew Control
----|--|----------------------------
EB |: |End Blanking
| |
====================================
The register fields are defined as follows:
===============================================================================================================
DES |These two bits determine the amount of skew of the 'display enable' signal. This skew control is
|needed to provide sufficient time for the CRT controller to read a character and attribute code from
|the video buffer, to gain access to the character generator, and go through the Horizontal PEL Pan-
|ning register in the attribute controller. Each access requires the 'display enable' signal to be skewed
|one character clock so that the video output is synchronized with the horizontal and vertical retrace
|signals. The skew values are shown below.
|
|DES Field
| 6 5 Amount of Skew
| 0 0 No character clock skew
| 0 1 One character clock skew
| 1 0 Two character clock skew
| 1 1 Three character clock skew
|
|Note: Character skew is not adjustable on the Type 2 video and the bits are ignored; however, pro-
|grams should set these bits for the appropriate skew to maintain compatibility.
|
----|----------------------------------------------------------------------------------------------------------
EB |These bits are the five low-order bits of a 6-bit value that is compared with the value in the Start
|Horizontal Blanking register to determine when the 'horizontal blanking' signal will go inactive. The
|most-significant bit is bit 7 in the End Horizontal Retrace register (index 0x05).
|To program these bits for a signal width of W, the following algorithm is used: the width W, in char-
|acter clock units, is added to the value from the Start Horizontal Blanking register. The six low-order
|bits of the result are the 6-bit value programmed.
|
===============================================================================================================
=============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|---------- Start Horizontal Retrace Pulse ===============================These bits are used to center the screen horizontally by specifying the character position where the 'horizontal retrace' signal goes active.
=========================
7 |6 |5 |4 |3 |2 |1 |0
----|--|--|--|--|--|--|--
EB5 |HRD |EHR
| |
=========================
End Horizontal Retrace Register, Index 0x05
=======================================
EB5 |: |End Horizontal Blanking, Bit 5
====|==|===============================
HRD |: |Horizontal Retrace Delay
----|--|-------------------------------
EHR |: |End Horizontal Retrace
| |
=======================================
The register fields are defined as follows:
=================================================================================================================
EB5 |This bit is the most significant bit (bit 5) of the end horizontal blanking value in the End Horizontal
|Blanking register (index 0x03).
|
----|------------------------------------------------------------------------------------------------------------
HRD |These bits control the skew of the 'horizontal retrace' signal. The value of these bits is the amount of
|skew provided (from 0 to 3 character clock units). For certain modes, the 'horizontal retrace' signal
|takes up the entire blanking interval. Some internal timings are generated by the falling edge of the
|'horizontal retrace' signal. To ensure that the signals are latched properly, the 'retrace' signal is
|started before the end of the 'display enable' signal and then skewed several character clock times to
|provide the Proper screen centering.
|
----|------------------------------------------------------------------------------------------------------------
EHR |These bits are compared with the Start Horizontal Retrace register to give a horizontal character
|count where the 'horizontal retrace' signal goes inactive.
|To program these bits with a signal width of W, the following algorithm is used: the width W, in
|character clock units, is added to the value in the Start Retrace register. The five low-order bits of the
|result are the 5-bit value programmed.
|
=================================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Vertical Total =======================These are the eight low-order bits of a 10-bit vertical total. The value for the vertical total is the number of horizontal raster scans on the display, including vertical retrace, minus 2. This value determines the period of the 'vertical retrace' signal.
Bits 8 and 9 are in the Overflow register (index 0x07).
============================================
7 |6 |5 |4 |3 |2 |1 |0
-----|-----|----|----|-----|-----|-----|----
VRS9 |VDE9 |VT9 |LC8 |VBS8 |VRS8 |VDE8 |VT8
| | | | | | |
============================================
Overflow Register, Index 0x07
============================================
VRS9 |: |Vertical Retrace Start, Bit 9
-----|--|-----------------------------------
VDE9 |: |Vertical Display Enable End, Bit 9
-----|--|-----------------------------------
VT9 |: |Vertical Total, Bit 9
-----|--|-----------------------------------
LC8 |: |Line Compare, Bit 8
-----|--|-----------------------------------
VBS8 |: |Vertical Blanking Start, Bit 8
-----|--|-----------------------------------
VRS8 |: |Vertical Retrace Start, Bit 8
-----|--|-----------------------------------
VDE8 |: |Vertical Display Enable End, Bit 8
-----|--|-----------------------------------
VT8 |: |Vertical Total, Bit 8
| |
============================================
The register fields are defined as follows: ====================================================================== VRS9 |Bit 9 of the Vertical Retrace Start register (index 0x10). =====|================================================================ VDE9 |Bit 9 of the Vertical Display Enable End register (index 0x12). -----|---------------------------------------------------------------- VT9 |Bit 9 of the Vertical Total register (index 0x06). -----|---------------------------------------------------------------- LC8 |Bit 8 of the Line Compare register (index 0x18). -----|---------------------------------------------------------------- VBS8 |Bit 8 of the Start Vertical Blanking register (index 0x15). -----|---------------------------------------------------------------- VRS8 |Bit 8 of the Vertical Retrace Start register (index 0x10). -----|---------------------------------------------------------------- VDE8 |Bit 8 of the Vertical Display Enable End register (index 0x12). -----|---------------------------------------------------------------- VT8 |Bit 8 of the Vertical Total register (index 0x06). ======================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |BP |SRS | | =======================
Preset Row Scan Register, Index 0x08
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
BP |: |Byte Panning
----|--|----------------------------
SRS |: |Starting Row Scan Count
| |
====================================
The register fields are defined as follows:
=========================================================================================================
BP |These two bits control byte panning in multiple shift modes. These bits are used in pel-panning op-
|erations. and should normally be set to 0.
|
====|====================================================================================================
SRS |These bits specify the row scan count for the row starting after a vertical retrace. The row scan
|counter is incremented every horizontal retrace time until the maximum row scan occurs. When the
|maximum row scan is reached, the row scan counter is cleared (not preset).
=========================================================================================================
Note: The CRT controller latches the start address at the start of the vertical retrace. These register values should be loaded during the active display time.
==============================
7 |6 |5 |4 |3 |2 |1 |0
----|----|-----|--|--|--|--|--
DSC |LC9 |VBS9 |MSL
| | |
==============================
Maximum Scan Line Register, Index 0x09
========================================
DSC |: |200 to 400 Line Conversion
-----|--|-------------------------------
LC9 |: |Line Compare, Bit 9
-----|--|-------------------------------
VBS9 |: |Start Vertical Blanking, Bit 9
-----|--|-------------------------------
MSL |: |Maximum Scan Line
| |
========================================
The register fields are defined as follows:
=============================================================================================================
DSC |When this bit is set to 1, 200-scan-line video data is converted to 400-scan-line output. To do this,
|the clock in the row scan counter is divided by 2, which allows the 200-line modes to be displayed
|as 400 lines on the display (this is called double scanning; each line is displayed twice). When this
|bit is set to 0, the clock to the row scan counter is equal to the horizontal scan rate.
|
=====|=======================================================================================================
LC9 |Bit 9 of the Line Compare register (index 0x18).
|
-----|-------------------------------------------------------------------------------------------------------
VBS9 |Bit 9 of the Start Vertical Blanking register (index 0x15).
|
-----|-------------------------------------------------------------------------------------------------------
MSL |These bits specify the number of scan lines per character row. The value of these bits is the maxi-
|mum row scan number minus 1.
=============================================================================================================
======================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|---|--|--|--|--|-- - |- |CO |RSCB | | | ========================
Cursor Start Register, Index 0x0A
=====================================
- |: |Set to 0, Undefined on Read
-----|--|----------------------------
CO |: |Cursor Off
-----|--|----------------------------
RSCB |: |Row Scan Cursor Begins
| |
=====================================
The register fields are defined as follows:
=================================================================================================================
CO |When set to 1, this bit disables the cursor.
|
=====|===========================================================================================================
RSCB |These bits specify the row within the character box where the cursor begins. The value of these bits
|is the first line of the cursor minus 1. When this value is greater than that in the Cursor End register,
|no cursor is displayed.
=================================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |CSK |RSCE | | =======================
Cursor End Register, Index 0x0B
=====================================
- |: |Set to 0, Undefined on Read
-----|--|----------------------------
CSK |: |Cursor Skew Control
-----|--|----------------------------
RSCE |: |Row Scan Cursor Ends
| |
=====================================
The register fields are defined as follows:
=============================================================================================================
CSK |These bits control the skew of the cursor. The skew value delays the cursor by the selected number
|of character clocks from 0 to 3. For example, a skew of 1 moves the cursor right one position on the
|screen.
|
=====|=======================================================================================================
RSCE |These bits specify the row within the character box where the cursor ends. If this value is less that
|the cursor start value, no cursor is displayed.
=============================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Start Address High =======================These are the eight high-order bits of a 16-bit value that specifies the starting address for the regenerative buffer. The start address points to the first address after the vertical retrace on each screen refresh.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Start Address Low =======================These are the eight low-order bits of the starting address for the regenerative buffer.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Cursor Location High =======================These are the eight high-order bits of the 16-bit cursor
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Cursor Location Low =======================These are the eight low-order bits of the cursor location.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Vertical Retrace Start =======================These are the eight low-order bits of the 9-bit start position for the 'vertical retrace' pulse; it is programmed in horizontal scan lines. Bit 8 is in the Overflow register (index 0x07).
============================== 7 |6 |5 |4 |3 |2 |1 |0 ---|----|----|----|--|--|--|-- PR |S5R |EVI |CVI |VRE | | | | ==============================
Vertical Retrace End Register, Index 0x11
==================================
PR |: |Protect Registers 0-7
----|--|--------------------------
S5R |: |Select 5 Refresh Cycles
----|--|--------------------------
EVI |: |Enable Vertical Interrupt
----|--|--------------------------
CVI |: |Clear Vertical Interrupt
----|--|--------------------------
VRE |: |Vertical Retrace End
| |
==================================
The register fields are defined as follows:
=====================================================================================================================
PR |When set to 1, this bit disables write access to the CRT controller registers at index 00 through 07.
|The line compare bit in the Overflow register (index 0x07) is not protected.
|
====|================================================================================================================
S5R |When set to 1, this bit generates five memory refresh cycles per horizontal line. When set to 0, this
|bit selects three refresh cycles. Selecting five refresh cycles allows use of the VGA chip with 15.75
|kHz displays. This bit should be set to 0 for supported operations.
|
----|----------------------------------------------------------------------------------------------------------------
EVI |When set to 0, this bit enables a vertical retrace interrupt. The vertical retrace interrupt is IRQ2. This
|interrupt level can be shared; therefore, to determine whether the video generated the interrupt,
|check the CRT interrupt bit in Input Status Register 0.
|
----|----------------------------------------------------------------------------------------------------------------
CVI |When set to 0, this bit clears a vertical retrace interrupt. At the end of the active vertical display
|time, a flip-flop is set to indicate an interrupt. An interrupt handler resets this flip-flop by first setting
|this bit to 0, then resetting it to 1.
|
----|----------------------------------------------------------------------------------------------------------------
VRE |The Vertical Retrace Start register is compared with these four bits to determine where the 'vertical
|retrace' signal goes inactive. It is programmed in units of horizontal scan lines. To program these bits
|with a signal width of W, the following algorithm is used: the width W, in horizontal scan units, is
|added to the value in the Start Vertical Retrace register. The four low-order bits of the result are the
|4-bit value programmed.
=====================================================================================================================
============================ 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|------- Vertical Display Enable End ============================These are the eight low-order bits of a 10-bit value that defines the vertical-display-enable end position. The two high-order bits are contained in the Overflow register (index 0x07). The 10-bit value is equal to the total number of scan lines minus 1.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Offset =======================These bits specify the logical line width of the screen. The starting memory address for the next character row is larger than the current character row by 2 or 4 times the value of these bits. Depending on the method of clocking the CRT controller, this address is either a word or doubleword address.
========================== 7 |6 |5 |4 |3 |2 |1 |0 --|---|----|--|--|--|--|-- - |DW |CB4 |SUL | | | ==========================
Underline Location Register, Index 0x14
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
DW |: |Doubleword Mode
----|--|----------------------------
CB4 |: |Count by 4
----|--|----------------------------
SUL |: |Start Underline
| |
====================================
The register fields are defined as follows:
===========================================================================================================
DW |When this bit is set to 1, memory addresses are doubleword addresses. See the description of the
|word/byte mode bit (bit 6) in the "CRT Mode Control Register" on page 220.
|
====|======================================================================================================
CB4 |When this bit is set to 1, the memory-address counter is clocked with the character clock divided by
|4, which is used when doubleword addresses are used.
|
----|------------------------------------------------------------------------------------------------------
SUL |These bits specify the horizontal scan line of a character row on which an underline occurs. The
|value programmed is the scan line desired minus 1.
===========================================================================================================
======================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|--- Start Vertical Blanking ========================These are the eight low-order bits of a 10-bit value that specifies the starting location for the 'vertical blanking' signal. Bit 8 is in the Overflow register (index 0x07) and bit 9 is in the Maximum Scan Line register (index 0x09). The 10-bit value is the horizontal scan line count where the 'vertical blanking' signal becomes active minus 1.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- End Vertical Blanking =======================This register specifies the horizontal scan count where the 'vertical blanking' signal becomes inactive. The register is Programmed in units of the horizontal scan line.
=====================================
7 |6 |5 |4 |3 |2 |1 |0
----|---|----|--|----|----|----|-----
RST |WB |ADW |- |CB2 |HRS |SRC |CMS0
| | | | | | |
=====================================
CRT Mode Control Register, Index 0x17
=====================================
- |: |Set to 0, Undefined on Read
-----|--|----------------------------
RST |: |Hardware Reset
-----|--|----------------------------
WB |: |Word/Byte Mode
-----|--|----------------------------
ADW |: |Address Wrap
-----|--|----------------------------
CB2 |: |Count by Two
-----|--|----------------------------
HRS |: |Horizontal Retrace Select
-----|--|----------------------------
SRC |: |Select Row Scan Counter
-----|--|----------------------------
CMS0 |: |Compatibility Mode Support
| |
=====================================
The register fields are defined as follows:
==================================================================================================================
RST |When set to 0, this bit disables the horizontal and vertical retrace signals and forces them to an inac-
|tive level. When set to 1, this bit enables the horizontal and vertical retrace signals. This bit does not
|reset any other registers or signal outputs.
|
-----|------------------------------------------------------------------------------------------------------------
WB |When this bit is set to 0, the word mode is selected. The word mode shifts the memory-address
|counter bits to the left by one bit; the most-significant bit of the counter appears on the least-signifi-
|cant bit of the memory address outputs.
|The doubleword bit in the Underline Location register (0x14) also controls the addressing. When the
|doubleword bit is 0, the word/byte bit selects the mode. When the doubleword bit is set to 1, the ad-
|dressing is shifted by two bits.
|When set to 1, bit 6 selects the byte address mode.
|
-----|------------------------------------------------------------------------------------------------------------
ADW |This bit selects the memory-address bit, bit MA 13 or MA 15, that appears on the output pin MA 0,
|in the word address mode. If the VGA is not in the word address mode, bit 0 from the address
|counter appears on the output pin, MA 0.
|When set to 1, this bit selects MA 15. In odd/even mode, this bit should be set to 1 because 256KB
|of video memory is installed on the system board. (Bit MA 13 is selected in applications where only
|64KB is present. This function maintains compatibility with the IBM Color/Graphics Monitor
|Adapter.)
|
-----|------------------------------------------------------------------------------------------------------------
CB2 |When this bit is set to 0, the address counter uses the character clock. When this bit is set to 1, the
|address counter uses the character clock input divided by 2. This bit is used to create either a byte or
|word refresh address for the display buffer.
|
-----|------------------------------------------------------------------------------------------------------------
HRS |This bit selects the clock that controls the vertical timing counter. The clocking is either the horizon-
|tal retrace clock or horizontal retrace clock divided by 2. When this bit is set to 1. the horizontal re-
|trace clock is divided by 2.
|Dividing the clock effectively doubles the vertical resolution of the CRT controller. The vertical
|counter has a maximum resolution of 1024 scan lines because the vertical total value is 10-bits wide.
|If the vertical counter is clocked with the horizontal retrace divided by 2, the vertical resolution is
|doubled to 2048 scan lines.
|
-----|------------------------------------------------------------------------------------------------------------
SRC |This bit selects the source of bit 14 of the output multiplexer. When this bit is set to 0, bit 1 of the
|row scan counter is the source. When this bit is set to 1, the bit 14 of the address counter is the
|source.
|
-----|------------------------------------------------------------------------------------------------------------
CMS0 |This bit selects the source of bit 13 of the output multiplexer. When this bit is set to 0, bit 0 of the
|row scan counter is the source, and when this bit is set to 1, bit 13 of the address counter is the
|source.
|The CRT controller used on the IBM Color/Graphics Adapter was capable of using 128 horizontal
|scan-line addresses. For the VGA to obtain 640-by-200 graphics resolution, the CRT controller is
|programmed for 100 horizontal scan lines with two scan-line addresses per character row. Row scan
|address bit 0 becomes the most-significant address bit to the display buffer. Successive scan lines of
|the display image are displaced in 8KB of memory. This bit allows compatibility with the graphics
|modes of earlier adapters.
==================================================================================================================
=======================
7 |6 |5 |4 |3 |2 |1 |0
--|--|--|--|--|--|--|--
Line Compare
=======================
This register contains the eight low-order bits of the 10-bit compare target. When the vertical counter reaches the target value, the internal start address of the line counter is cleared. This creates a split screen where the lower screen is immune to scrolling. Bit 8 is in the Overflow register (index 0x07), and bit 9 is in the Maximum Scan Line register (index 0x09).
Table 366. Graphics Controller Registers ================================= Register Name |Address |Index =================|========|====== Address |0x03CE |- -----------------|--------|------ Set/Reset |0x03CF |0x0 -----------------|--------|------ Enable Set/Reset |0x03CF |0x01 -----------------|--------|------ Color Compare |0x03CF |0x02 -----------------|--------|------ Data Rotate |0x03CF |0x03 -----------------|--------|------ Read Map Select |0x03CF |0x04 -----------------|--------|------ Graphics Mode |0x03CF |0x05 -----------------|--------|------ Miscellaneous |0x03CF |0x06 -----------------|--------|------ Color Don't Care |0x03CF |0x07 -----------------|--------|------ Bit Mask |0x03CF |0x08 =================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |- |- |- |Index =======================This register is loaded with the index value that points to the desired data register within the graphics controller.
=============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|----|----|----|---- - |- |- |- |SR3 |SR2 |SR1 |SR0 | | | | | | | ===============================
Set/Reset Register, Index 0x00
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
SR3 |: |Set/Reset Map 3
----|--|----------------------------
SR2 |: |Set/Reset Map 2
----|--|----------------------------
SR1 |: |Set/Reset Map 1
----|--|----------------------------
SR0 |: |Set/Reset Map 0
| |
====================================
The register fields are defined as follows:
===============================================================================================================
SR* |When write mode 0 is selected, the system writes the value of each set/reset bit to its respective
|memory map. For each write operation, the set/reset bit, if enabled, is written to all eight bits within
|that map. Set/reset operation can be enabled on a map-by-map basis through the Enable Set/Reset
|register.
===============================================================================================================
=================================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|-----|-----|-----|----- - |- |- |- |ESR3 |ESR2 |ESR1 |ESR0 | | | | | | | ===================================
Enable Set/Reset Register, Index 0x01
=====================================
- |: |Set to 0, Undefined on Read
-----|--|----------------------------
ESR3 |: |Enable Set/Reset Map 3
-----|--|----------------------------
ESR2 |: |Enable Set/Reset Map 2
-----|--|----------------------------
ESR1 |: |Enable Set/Reset Map 1
-----|--|----------------------------
ESR0 |: |Enable Set/Reset Map 0
| |
=====================================
The register fields are defined as follows:
============================================================================================================
ESR* |These bits enable the set/reset function used when write mode 0 is selected in the Graphics Mode
|register (index 0x05). When the bit is set to 1, the respective memory map receives the value speci-
|fied in the Set/Reset register. When Set/Reset is not enabled for a map, that map receives the value
|sent by the system.
============================================================================================================
=============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|----|----|----|---- - |- |- |- |CC3 |CC2 |CC1 |CC0 | | | | | | | ===============================
Color Compare Register, Index 0x02
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
CC3 |: |Color Compare Map 3
----|--|----------------------------
CC2 |: |Color Compare Map 2
----|--|----------------------------
CC1 |: |Color Compare Map 1
----|--|----------------------------
CC0 |: |Color Compare Map 0
| |
====================================
The register fields are defined as follows:
=============================================================================================================
CC* |These bits are the 4-bit color value to be compared when the read mode bit in the Graphics Mode
|register is set to 1. When the system does a memory read, the data returned from the memory cycle
|will be a 1 in each bit position where the four maps equal the Color Compare register. If the read
|mode bit is 0, the data is returned without comparison.
|All bits of the corresponding map's byte are compared with the color compare bit. Each of the eight
|bit positions in the selected byte are compared across the four maps, and a 1 is returned in each posi-
|tion where the bits of all four maps equal their respective color compare values.
=============================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |- |- |FS |RC | | | | =======================
Data Rotate Register, Index 0x03 =================================== - |: |Set to 0, Undefined on Read ---|--|---------------------------- FS |: |Function Select ---|--|---------------------------- RC |: |Rotate Count | | ===================================
The register fields are defined as follows: ================================================================================================================== FS |Data written to the video buffer can be operated on logically by data already in the system latches. |The Function Select field determines whether and how this is done. |Data can be any of the choices selected by the write mode bits except system latches, which cannot |be modified. If rotated data is selected also, the rotate is performed before the logical operation. The |logical operations selected are shown in the following table. | |FS Field | 4 3 Function | 0 0 Data Unmodified | 0 1 Data ANDed with Latched Data | 1 0 Data ORed with Latched Data | 1 1 Data XORed with Latched Data | ---|-------------------------------------------------------------------------------------------------------------- RC |In write mode 0, these bits select the number of positions the system data is rotated to the right dur- |ing a system Memory Write operation. To write data that is not rotated in mode 0, all bits are set to 0. | ==================================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |- |- |- |- |- |MS | | | | | | =======================
Read Map Select Register, Index 0x04 =================================== - |: |Set to 0, Undefined on Read ---|--|---------------------------- MS |: |Map Select | | ===================================
The register field is defined as follows: =========================================================================================================== MS |These bits select the memory map for system read operations. This register has no effect on the color |compare read mode. In odd/even modes, the value can be a binary 00 or 01 to select the chained |maps 0, 1 and the value can be a binary 10 or 11 to select the chained maps 2, 3. ===========================================================================================================
============================= 7 |6 |5 |4 |3 |2 |1 |0 --|-----|---|---|---|--|--|-- - |C256 |SR |OE |RM |- |WM | | | | | | =============================
Graphics Mode Register, Index 0x05
=====================================
- |: |Set to 0, Undefined on Read
-----|--|----------------------------
C256 |: |256 - Color Mode
-----|--|----------------------------
SR |: |Shift Register Mode
-----|--|----------------------------
OE |: |Odd/Even
-----|--|----------------------------
RM |: |Read Mode
-----|--|----------------------------
WM |: |Write Mode
| |
=====================================
The register fields are defined as follows:
===================================================================================================================
C256 |When set to 0, this bit allows bit 5 to control the loading of the shift registers. When set to 1, this bit
|causes the shift registers to be loaded in a manner that supports the 256-color mode.
|
-----|-------------------------------------------------------------------------------------------------------------
SR |When set to 1, this bit directs the shift registers in the graphics controller to format the serial data
|stream with even-numbered bits from both maps on even-numbered maps, and odd-numbered bits
|from both maps on the odd-numbered maps. This bit is used for modes 4 and 5.
|
-----|-------------------------------------------------------------------------------------------------------------
OE |When set to 1, this bit selects the odd/even addressing mode used by the IBM Color/Graphics Mon-
|itor Adapter. Normally, the value here follows the value of Memory Mode register bit 2 in the se-
|quencer.
|
-----|-------------------------------------------------------------------------------------------------------------
RM |When this bit is set to 1, the system reads the results of the comparison of the four memory maps and
|the Color Compare register.
|When this bit is set to 0, the system reads data from the memory map selected by the Read Map Se-
|lect register, or by the two low-order bits of the memory address (this selection depends on the
|chain-4 bit in the Memory Mode register of the sequencer).
|
-----|-------------------------------------------------------------------------------------------------------------
WM |The write mode selected and its operation are defined below. The logic operation specified by the
|function select bits is performed on system data for modes 0, 2, and 3.
===================================================================================================================
================================================================================
WM Field |Mode Description
=========|======================================================================
00 |Each memory map is written with the system data rotated by the
|count in the Data Rotate register. If the set/reset function is en-
|abled for a specific map, that map receives the 8-bit value con-
|tained in the Set/Reset register.
---------|----------------------------------------------------------------------
01 |Each memory map is written with the contents of the system
|latches. These latches are loaded by a system Read operation.
---------|----------------------------------------------------------------------
10 |Memory map n (0 through 3) is filled with eight bits of the value
|of data bit n.
---------|----------------------------------------------------------------------
11 |Each memory map is written with the 8-bit value contained in the
|Set/Reset register for that map (the Enable Set/Reset register has
|no effect). Rotated system data is ANDed with the Bit Mask reg-
|ister to form an 8-bit value that performs the same function as the
|Bit Mask register in write modes 0 and 2 (see also "Bit Mask
|Register" on page 226).
================================================================================
========================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|---|--- - |- |- |- |MM |OE |GM | | | | | | =========================
Miscellaneous Register, Index 0x06 =================================== - |: |Set to 0, Undefined on Read ---|--|---------------------------- MM |: |Memory Map ---|--|---------------------------- OE |: |Odd/Even ---|--|---------------------------- GM |: |Graphics Mode | | ===================================
The register fields are defined as follows: =========================================================================================================== MM |These bits control the mapping of the regenerative buffer into the system address space. The bit |functions are defined below. | |MM Field | 3 2 Addressing Assignment | 0 0 A0000 for 128KB | 0 1 A0000 for 64KB | 1 0 B0000 for 32 KB | 1 1 B8000 for 32 KB | ---|------------------------------------------------------------------------------------------------------- OE |When set to 1, this bit directs the system address bit, A0, to be replaced by a higher-order bit. The |odd map is then selected when A0 is 1, and the even map when A0 is 0. | ---|------------------------------------------------------------------------------------------------------- GM |This bit controls alphanumeric mode addressing. When set to 1, this bit selects graphics modes, |which also disables the character generator latches. ===========================================================================================================
=========================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|---|---|---|--- - |- |- |- |M3 |M2 |M1 |M0 | | | | | | | ===========================
Color Don't Care Register, Index 0x07 =================================== - |: |Set to 0, Undefined on Read ---|--|---------------------------- M3 |: |Compare Map 3 ---|--|---------------------------- M2 |: |Compare Map 2 ---|--|---------------------------- M1 |: |Compare Map 1 ---|--|---------------------------- M0 |: |Compare Map 0 | | ===================================
The register fields are defined as follows: ========================================================================================================= M* |These bits select whether a map is going to participate in the color compare cycle. When the bit is |set to 1, the bits in that map are compared. =========================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Bit Mask =======================When the bit is set to 1, the corresponding bit position in each map can be changed. When the bit set to 0, the bit position in the map is masked to prevent change, provided that the location being written was the last location read by the system microprocessor.
Table 367. Attribute Controller Registers:
===================================================
Register Name |Write |Read |Index
|Address |Address |
=======================|========|========|=========
Address |0x03C0 |0x03C0 |-
-----------------------|--------|--------|---------
Internal Palette |0x03C0 |0x03C1 |0x0-0x0F
-----------------------|--------|--------|---------
Attribute Mode Control |0x03C0 |0x03C1 |0x10
-----------------------|--------|--------|---------
Overscan Color |0x03C0 |0x03C1 |0x11
-----------------------|--------|--------|---------
Color Plane Enable |0x03C0 |0x03C1 |0x12
-----------------------|--------|--------|---------
Horizontal PEL Panning |0x03C0 |0x03C1 |0x13
-----------------------|--------|--------|---------
Color Select |0x03C0 |0x03C1 |0x14
===================================================
========================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|-----|--|--|--|--|-- - |- |IPAS |Index | | | ==========================
Address Register
=========================================
- |: |Set to 0, Undefined on Read
-----|--|--------------------------------
IPAS |: |Internal Palette Address Source
| |
=========================================
The register fields are defined as follows:
======================================================================================================================
IPAS |This bit is set to 0 to load color values to the registers in the internal palette. It is set to 1 for normal
|operation of the attribute controller.
|Note: Do not access the internal palette while this bit is set to 1. While this bit is 1, the Type 1 video
|subsystem disables accesses to the palette; however, the Type 2 does not, and the actual color value
|addressed cannot be ensured.
|
------|---------------------------------------------------------------------------------------------------------------
Index |These bits contain the index to the data registers in the attribute controller.
======================================================================================================================
============================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|---|---|---|---|---|--- - |- |P5 |P4 |P3 |P2 |P1 |P0 | | | | | | | =============================
Internal Palette Registers
=========================================
- |: |Set to 0, Undefined on Read
---------|--|----------------------------
P5 to P0 |: |Palette Data
| |
=========================================
The register fields are defined as follows:
==============================================================================================================
P5-P0 |These 6-bit registers allow a dynamic mapping between the text attribute or graphic color input
|value and the display color on the CRT screen. When set to 1, this bit selects the appropriate color.
|The Internal Palette registers should be modified only during the vertical retrace interval to avoid
|problems with the displayed image. These internal palette values are sent off-chip to the video DAC,
|where they serve as addresses into the DAC registers.
| Bit Color
| 0 Blue
| 1 Green
| 2 Red
| 3 Secondary Blue
| 4 Secondary Green
| 5 Secondary Red
==============================================================================================================
Software Implementation Note: These registers can be accessed only when bit 5 in the Address register is set to 0. When the bit is 1, writes are "don't care" and reads return undefined data.
============================== 7 |6 |5 |4 |3 |2 |1 |0 ---|---|---|--|---|----|---|-- PS |PW |PP |- |EB |ELG |ME |G | | | | | | | ==============================
Attribute Mode Control Register
=================================================
- |: |Set to 0, Undefined on Read
----|--|-----------------------------------------
PS |: |P5, P4 Select
----|--|-----------------------------------------
PW |: |PEL Width
----|--|-----------------------------------------
PP |: |PEL Panning Compatibility
----|--|-----------------------------------------
EB |: |Enable Blink/Select Background Intensity
----|--|-----------------------------------------
ELG |: |Enable Line Graphics Character Code
----|--|-----------------------------------------
ME |: |Mono Emulation
----|--|-----------------------------------------
G |: |Graphics/Alphanumeric Mode
| |
=================================================
The register fields are defined as follows:
====================================================================================================================
PS |This bit selects the source for the P5 and P4 video bits that act as inputs to the video DAC. When
|this bit is set to 0, P5 and P4 are the outputs of the Internal Palette registers. When this bit is set to 1,
|P5 and P4 are bits 1 and 0 of the Color Select register.
|
----|---------------------------------------------------------------------------------------------------------------
PW |When this bit is set to 1, the video data is sampled so that eight bits are available to select a color in
|the 256-color mode (0x13). This bit is set to 0 in all other modes.
|
----|---------------------------------------------------------------------------------------------------------------
PP |When this bit is set to 1, a successful line-compare in the CRT controller forces the output of the
|PEL Panning register to 0 until a vertical synchronization occurs, at which time the output returns to
|its programmed value. This bit allows a selected portion of a screen to be panned.
|When this bit is set to 0, line compare has no effect on the output of the PEL Panning register.
|
----|---------------------------------------------------------------------------------------------------------------
EB |When this bit is set to 0, the most-significant bit of the attribute selects the background intensity (al-
|lows 16 colors for background). When set to 1, this bit enables blinking.
|
----|---------------------------------------------------------------------------------------------------------------
ELG |When this bit is set to 0, the ninth dot will be the same as the background. When set to 1, this bit en-
|ables the special line-graphics character codes for the monochrome emulation mode. This emulation
|mode forces the ninth dot of a line graphic character to be identical to the eighth dot of the character.
|The line-graphics character codes for the monochrome emulation mode are 0xC0 through 0xDF.
|For character fonts that do not utilize these line-graphics character codes, bit 2 should be set to 0 to
|prevent unwanted video information from displaying on the CRT screen.
|BIOS will set this bit, the correct dot clock, and other registers when the 9-dot alphanumeric mode is
|selected.
|
----|---------------------------------------------------------------------------------------------------------------
ME |When this bit is set to 1, monochrome emulation mode is selected. When this bit is set to 0, color
|emulation mode is selected.
|
----|---------------------------------------------------------------------------------------------------------------
G |When set to 1, this bit selects the graphics mode of operation.
====================================================================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Overscan Color =======================These bits select the border color used in the 80-column alphanumeric modes and in the graphics modes other than modes 4, 5, and D. (Selects a color from one of the DAC registers.)
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- | | | |ECP | | | | =======================
Color Plane Enable Register
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
ECP |: |Enable Color Plane
| |
====================================
The register field is defined as follows: =============================================================================== ECP |Setting a bit to 1, enables the corresponding display-memory color plane. ===============================================================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- | | | |HPP | | | | =======================
Attribute Mode Control Register
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
HPP |: |Horizontal PEL Panning
| |
====================================
The register field is defined as follows:
================================================================================================================
HPP |These bits select the number of pels that the video data is shifted to the left. PEL panning is available
|in both alphanumeric and graphics modes. The following table shows the number of bits shifted for
|each mode.
|
================================================================================================================
Table 368. Image Shifting
=====================================================
Register Value |Number of Pels Shifted to the Left
|-------------------------------------
|Mode Hex |A/N |All Other
|13 |Modes* |Modes
===============|=========|=======|===================
0 |0 |1 |0
---------------|---------|-------|-------------------
1 |- |2 |1
---------------|---------|-------|-------------------
2 |1 |3 |2
---------------|---------|-------|-------------------
3 |- |4 |3
---------------|---------|-------|-------------------
4 |2 |5 |4
---------------|---------|-------|-------------------
5 |- |6 |5
---------------|---------|-------|-------------------
6 |3 |7 |6
---------------|---------|-------|-------------------
7 |- |8 |7
---------------|---------|-------|-------------------
8 |- |0 |-
=====================================================
* Only mode 7 and the A/N modes with 400 scan lines.
=====================================================
=============================== 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|----|----|----|---- - |- |- |- |SC7 |SC6 |SC5 |SC4 | | | | | | | ===============================
Color Select Register
====================================
- |: |Set to 0, Undefined on Read
----|--|----------------------------
SC7 |: |S_color 7
----|--|----------------------------
SC6 |: |S_color 6
----|--|----------------------------
SC5 |: |S_color 5
----|--|----------------------------
SC4 |: |S_color 4
| |
====================================
The register fields are defined as follows:
==================================================================================================================
SC7, SC6 |In modes other than mode 13 hex, these are the two most-significant bits of the 8-bit digital color
|value to the video DAC. In mode 13 hex, the 8-bit attribute is the digital color value to the video
|DAC. These bits are used to rapidly switch between sets of colors in the video DAC.
|
---------|--------------------------------------------------------------------------------------------------------
SC5, SC4 |These bits can be used in place of the P4 and P5 bits from the Internal Palette registers to form the
|8-bit digital color value to the video DAC. Selecting these bits is done in the Attribute Mode Control
|register (index 0x10). These bits are used to rapidly switch between colors sets within the video
|DAC.
|
==================================================================================================================
Table 369. DAC Registers
===============================================
Register Name |Read/ |Address
|Write |
=============================|=======|=========
Palette Address (Write Mode) |R/W |0x03C8
-----------------------------|-------|---------
Palette Address (Read Mode) |W |0x03C7
-----------------------------|-------|---------
DAC State |R |0x03C7
-----------------------------|-------|---------
Palette Data |R/W |0x03C9
-----------------------------|-------|---------
Pel Mask |R |0x03C6
===============================================
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Palette Address =======================This register contains the 8-bit address used to access the 256 color registers during a write operation. Color data from the Palette Data Register is loaded into the palette registers in three separate output cycles per write operation. At the end of the third output to the Palette Data Register, the Palette Address Register will automatically increment.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Palette Address =======================This register contains the 8-bit address used to access the 256 color registers during a read operation. Color data from the palette registers is loaded into the Palette Data Register in three separate output cycles per write operation. At the end of the third output to the Palette Data Register, the Palette Address Register will automatically increment.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- - |- |- |- |- |- |STA =======================This is a read-only register that returns the last active operation in bits 1 and 0. If the last operation was a read operation, both bits are set to 1. If the last operation was a write, both bits are set to 0.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Palette Data =======================The Palette Data Register is really 18 bits wide to correspond to the three 6-bit RGB representations in the palette registers. Since the system interface is 8 bits, three read/write operations are needed to access this register for each palette register.
======================= 7 |6 |5 |4 |3 |2 |1 |0 --|--|--|--|--|--|--|-- Pel Mask =======================This read only register is initialized by the mode set software and should not be further modified.
The general registers do not share a common address; they each have their own I/O address.
See "Video DAC to System Interface" on page 232 for details on programming the video DAC.
===========================
0000H |
------|--------------------
|Screen B
|Buffer Storage Area
------|--------------------
0FFFH |
------|--------------------
1000H |
------|--------------------
|Screen A
|Buffer Storage Area
------|--------------------
7FFFH |
|
===========================
The Line Compare register of the CRT controller performs the split screen function. The CRT controller has an internal horizontal scan line counter and logic that compares the counter value to the value in the Line Compare register and clears the memory address generator when a comparison occurs. The linear address generator then sequentially addresses the display buffer starting at location 0. Each subsequent row address is determined by the 16-bit addition of the start-of-line latch and the Offset register.