Scache Status Register (SC_STAT)
Address: IPR CBU, FF.FFF0.00E8
The Scache status (SC_STAT) register is a read-only register. If an Scache tag or data parity error is detected during an Scache lookup, the SC_STAT is locked. Any PALcode read of this register unlocks SC_ADDR and SC_STAT. |
| SC_SCND_ERR | <16>R |
When set, this bit indicates that an Scache transaction resulted in a parity error while
SC_TPERR or SC_DPERR was already set from an earlier transaction. |
| SC_CMD<4:0> | <15:11>R |
This field indicates the Scache transaction that resulted in an Scache tag or data
parity error.
| Source Encoding | |
|---|
| <4:3> | <2:0> | Description |
|---|
| 1x | 110 | Set shared from system. |
| 1x | 101 | Read dirty from system. |
| 1x | 100 | Invalidate from system. |
| 1x | 001 | Scache victim. |
| 00 | 001 | Scache IREAD. |
| 01 | 001 | Scache DREAD. |
| 01 | 011 | Scache DWRITE. |
|
| SC_DPERR<7:0> | <10:03>R |
When set, these bits indicate that an Scache read transaction resulted in a data parity error. Each bit indicates that one or more bytes within a longword had the data parity error.
|
| SC_TPERR<2:0> | <02:00>R |
When set, these bits indicate that an Scache tag lookup resulted in a tag parity error, and they identify the set with the error. |