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Address: 87.6000.0480, 87.6000.0580, 87.6000.0680, 87.6000.0780 The Translated Base Register (TBR) is used to map PCI addresses into memory. There are four TBRs: TBR0, TBRl, TBR2, and TBR3, one for each window. If the Scatter/Gather bit of the Window Base Register is set, then the TBR provides the base address of the Scatter/Gather map for this window. If the Scatter/Gather bit is clear, the TBR provides the base physical address of this window. The TBR registers should not be modified unless software ensures that no PCI traffic is targeted for the window being modified. | ||
| T_BASE <33:10> | <31:8> RW |
If Scatter/Gather mapping is disabled, T_BASE<33:10> specifies the base CPU address of the translated PCI address for the PCI Target Window. If Scatter/Gather mapping is enabled, T_BASE<33:10> specifies the base CPU address for the Scatter/Gather map table for the PCI Target Window |
| Reserved | <7:0> RO |
N/A |