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Address: 87.4000.8240 The PYXIS_STATUS register contains information pertinent to the state of the PYXIS at the time an error occurred. You can use this register, along with the error registers, in isolating the error condition and determining a proper recovery action. | ||
| Reserved | <31:12>RO | N/A |
| TLB_MISS | <11>RO | If set, then a TLB MISS refill was in progress when this error occurred. |
| Reserved | <10:8>RO | N/A |
| IOA_VALID <3:0> | <7:4>RO | Valid bits for the I/O command/address queue. |
| Reserved | <3:2>RO | N/A |
| PCI_STATUS<1> | <1>RO | If set, then the PCI master state machine is active. |
| PCI_STATUS<0> | <0>RO | If set, then the PCI target state machine is active. |