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Address: 87.5000.0300 The refresh timing register contains refresh timing information used to simultaneously refresh all bank using CAS-before-RAS refresh. Therefore, these parameters should be programmed to the most conservative value across all bank. The observed refresh interval may be greater than the value programmed in REF_INTERVAL by the number of memClk cycles required to perform a read or write plus a RAS precharge interval. The programmer must account for this behavior when choosing the value of REF_INTERVAL. All the timing parameters are in multiples of memClk cycles. The parameters have a minimum value that is added to the programmed value. The programmer should be careful to subtract this value from the desired value before programming it to the register. | ||
| Reserved | <31:15>RO | N/A |
| RTR_FORCE _REF | <15>RW | Force refresh. Writing a 1 to this bit causes a single memory refresh. Reads as 0. Resets the internal refresh interval counter. Do not change the other timings in this register while setting this bit. |
| Reserved | <14:13>RO | Always zero fill. |
| REF_ INTERVAL | <12:7>RW | Refresh interval. Multiplied by 64 to generate number of memClk cycles between refresh requests. A programmed value of zero (0) is illegal. |
| REFRESH _WIDTH | <6:4>RW | Number of cycles for refresh command before any other command is attempted. This value corresponds to the RAS Active time (min) parameter in the vendor SDRAM specification. |
| Reserved | <3:0>RO | N/A |