|
Address: 87.4000.4000 The PERF_MONITOR CSR is really two 16-bit counters that can be programmed to count a variety of events. Setting up the counters is done via the PERF_CONTROL CSR. Each counter can be programmed to count events such as EV56 Read Misses received by PYXIS or DMA Writes. The PERF_MONITOR can also be set up as a single 32-bit counter (by telling the high_count to count the low_counter overflow). | ||
| HIGH_COUNT | <31:16>RO | This is the value of the high counter. |
| LOW_COUNT | <15:0>RO | This is the value of the low counter. |