PCI Error Register 2 (PCI_ERR2)

Address: 87.4000.8880 The PCI_ERR2 register is used by the PYXIS to log PCI address <31:0> pertaining to an error condition logged in PCI_ERR0. This register is locked whenever the PYXIS detects an error. This register always captures PCI address<31:0>, even for a DMA DAC cycle. The most significant PCI address<39:32> can be obtained from the W_DAC register; PCI address<63:40> had to be read for the PYXIS to hit on the DAC cycle. The register is unlocked when the error bits in the PYXIS_ERR CSR have all been cleared. Contents of this register are unpredictable when not locked. The PCI_ERR2 register and some fields in PCI_ERR0 (PCI_DAC, PCI CMD, TARGET_STATE, and MASTER STATE) hold information related to the following errors associated with the PCI bus: PCI Data Parity error (PYXIS_ERR<5>) PCI Address Parity Error (PYXIS_ERR<6>) PCI Master Abort (PYXIS_ERR<7>) PCI Target Abort (PYXIS_ERR<8>) IOA Timeout (PYXIS_ERR<11>)
PCI_ADDRESS <31:0>	<31:0>RO	Contains the PCI address <31:0>.