PCI Error Register 0 (PCI_ERR0)
Address: 87.4000.8800
The PCI_ERR0 register is used by the PYXIS to log information pertaining to the state of the PCI interface when an error condition is detected by PYXIS. The CSR is locked, as are all PYXIS error registers, when the PYXIS detects an error. The CSR is unlocked when the PYXIS_ERR_CSR is cleared. When the register is not locked, the contents are unpredictable.
The data in the WINDOW, DMA_DAC, and DMA_CMD fields is associated with the address stored in the PCI_ERR1 register. This group and PCI_ERR1 hold information related to the following errors associated with the memory while the PYXIS is handling a DMA:
- Correctable ECC error (PYXIS_ERR<0>)
- Uncorrectable ECC error (PYXIS_ERR<l>)
- Access to nonexistent memory (PYXIS_ERR<3>)
- Invalid Page Table entry (PYXIS_ERR<9>)
The data in the PCI_DAC, PCI_CMD, TARGET_STATE, and MASTER_STATE fields is
associated with the address stored in the PCI_ERR2 register. This group and the
PCI_ERR2 register hold information related to the following error conditions associated
with the PCI bus:
- PCI Data Parity error(PYXIS ERR<5>)
- PCI Address Parity Error (PYXIS_ERR<6>)
- PCI Master Abort (PYXIS_ERR<7>)
- PCI Target Abort (PYXIS_ERR<8>)
- IOA Timeout (PYXIS_ERR<11>)
The LOCK_STATE field is general information about the current state of PYXIS not
specifically associated with either PCI_ERR1 or PCI_ERR2.
|
| Reserved | <31:29>RO |
N/A |
| PCI_DAC | <28>RO |
If set then the current PCI command is a dual address cycle command. |
| PCI_CMD | <27:24>RO |
The current PCI command. |
TARGET
_STATE | <23:20>RO |
| 0 | Idle |
| 1 | Busy |
| 2 | Read Data Cycle |
| 3 | Write Data Cycle |
| 4 | Read Stop Cycle |
| 5 | Write Stop Cycle |
| 6 | Read Turnaround Cycle |
| 7 | Write Turnaround Cycle |
| 8 | Read Delay Cycle |
| 9 | Write Delay Cycle |
|
MASTER
_STATE | <19:16>RO |
| 0 | Idle |
| 1 | Drive Bus |
| 2 | Address Step Cycle |
| 3 | Address Cycle |
| 4 | Data Cycle |
| 5 | Last Read Data Cycle |
| 6 | Last Write Data Cycle |
| 7 | Read Stop Cycle |
| 8 | Write Stop Cycle |
| 9 | Read Turnaround Cycle |
| A | Write Turnaround Cycle |
| B | Reserved |
| C | Reserved |
| D | Reserved |
| E | Reserved |
| F | Unknown State |
|
| Reserved | <15:12>RO |
N/A |
| WINDOW | <11:8>RO |
Indicates which window (if any) was selected by the PCI address.
| 0000 | No window active |
| 0001 | Window 0 hit |
| 0010 | Window 1 hit |
| 0100 | Window 2 hit |
| 1000 | Window 3 hit |
|
| Reserved | <7:6>RO |
N/A |
| DMA_DAC | <5>RO |
If set, then the current DMA is a dual address cycle command. |
| Reserved | <4>RO |
N/A |
| DMA_CMD | <3:0>RO |
The PCI command of the current DMA. |