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Address: 87.4000.4040 The PERF_CONTROL CSR controls the performance monitor. | ||
| HIGH_COUNT _START | <31>RW | 0: Do not count. Keep current values. 1: Start counting. |
| HIGH_ERR _STOP | <30>RW | If PYXIS detects an error and this bit is set, then stop counting. |
| HIG_COUNT _CLR | <29>WO | Write a 1 to clear the high counter. |
| HIGH_COUNT _CYCLES | <28>RW | When set to a one, the number of cycles that the high_select event is asserted is counted. When set to zero, the number of low to high transitions are counted. |
| Reserved | <27:19>RO | N/A |
| HIGH_SELECT | <18:16>RW | Enables certain debug features. |
| LOW_COUNT _START | <15>RW | 0: Do not count. Keep current values. 1: Start counting. |
| LOW_ERR _STOP | <14>RW | If PYXIS detects an error and this bit is set, then stop counting. |
| LOW_COUNT _CLR | <13>WO | Write a 1 (one) to clear the low counter. |
| LOW_COUNT _CYCLES | <12>RW | When set to a1 (one), the number of cycles that the low_select event is asserted is counted. When set to 0 (zero), the number of low to high transitions are counted. |
| Reserved | <11:3>RO | N/A |
| LOW_SELECT | <2:0>RW | Enables certain debug features. |