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Address: 87.5000.0000 The memory control register contains all of the functions necessary to set up and configure the base control functions of the memory subsystem. | ||
| Reserved | <31:30>RO | N/A |
| DRAM_MODE | <29:16>RW | This field is subdivided into three fields that are forwarded directly to the memory DIMMs. Refer to the individual DIMM specification for details. |
| DRAM_CLK _AUTO | <15>RW | When set, automatic suppression of DRAM_CLK when there is no memory controller activity for eight cycles is enabled. |
| CKE_AUTO | <14>RW | When set, the automatic de-assertion of DRAM_CKE when there is no memory controller activity for eight cycles is enabled. |
| SEQ_TRACE | <13>RW | Enable the output of the memory sequencer out to the DRAM address lines. Intended for debug. |
| OVERLAP _DISABLE | <12>RW | When asserted, causes the memory controller to operate in a conservative mode. New memory transactions will not be started until the data cycles of the previous transactions have completed. |
| PIPELINED _BCACHE | <11>RW | When asserted, this causes the PYXIS to use the CLK edge one cycle after DACK to capture read data rather than using SRAM_CLK_IN. |
| BCACHE _ENABLE | <10>RW | When set, BCACHE-related functions in the MCTL, such as IDLE_BC assertion, snoop type for certain DMA functions and assertion of DBUS_REQ to acquire the bus, are enabled. If BCACHE_ENABLE is not asserted, the CACHE_ISOLATE signal is kept asserted |
| BCACHE _TYPE | <9>RO | Indicates the type of a Backup Cache. A 0 (zero) indicates a nonpipelined BCACHE, and a 1 indicates a pipelined BCACHE. |
| SERVER _MODE | <8>RO | Indicates the operating configuration of the system. A 0 (zero) indicates WORKSTATION mode, and a 1 indicates SERVER mode. |
| Reserved | <7:1>RO | N/A |
| MODE_REQ | <0>RW | Causes the PYXIS to send the Mode Register Set command to the memory DIMMs. |