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Address: 87.5000.0040 This register controls the DRAM_CLK pins and SRAM_CLK pins. These bits are initialized to "1" at reset. Note that DRAM_CLK[12] generally should not be turned off since this bit is connected to DRAM_CLK_IN and controls the operation of the clock delay circuit. . When a bit is programmed to a 0 (zero), the corresponding output is driven low. Any clock that is not used should be turned off, the corresponding bit set to 0 (zero). The will limit power dissipation and lower the EMI. | ||
| MCMR<15> | <15>RW | SRAM_CLK[2] |
| MCMR<14> | <14>RW | SRAM_CLK[1] |
| MCMR<13> | <13>RW | SRAM_CLK[0] |
| MCMR<12> | <12>RW | DRAM_CLK[12] |
| MCMR<11> | <11>RW | DRAM_CLK[11] |
| MCMR<10> | <10>RW | DRAM_CLK[10] |
| MCMR<9> | <9>RW | DRAM_CLK[9] |
| MCMR<8> | <8>RW | DRAM_CLK[8] |
| MCMR<7> | <7>RW | DRAM_CLK[7] |
| MCMR<6> | <6>RW | DRAM_CLK[6] |
| MCMR<5> | <5>RW | DRAM_CLK[5] |
| MCMR<4> | <4>RW | DRAM_CLK[4] |
| MCMR<3> | <3>RW | DRAM_CLK[3] |
| MCMR<2> | <2>RW | DRAM_CLK[2] |
| MCMR<1> | <1>RW | DRAM_CLK[1] |
| MCMR<0> | <0>RW | DRAM_CLK[0] |