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Address: 87.4000.00C0 The PCI Latency Register (PCI_LAT) Contains the PCI Master latency timeout value expressed in PCI clock cycles. | ||
| MSTR_LAT | <15:8>RW | PCI Master latency timer in PCI clock cycles. |
| MSTR_RET | <7:4>RW | PCI Master retry count in multiples of four PCI clock cycles. This is the number of cycles that the PYXIS will wait until it retries after it has stopped. The recommended value is zero (0). |
| TRGT_RET | <3:0>RW | PCI target retry count in PCI clock cycles. This is the number of cycles that the PYXIS will wait after a resource busy until it will stop. The value should be tuned for performance. |