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Address: 87.5000.0200 The global timing register contains parameters that are common to all memory transactions including the Bcache. Each parameter counts dramClk cycles. All pins on the memory interface are referenced to dramClk rising. | ||
| Reserved | <31:11>RO | N/A |
| IDLE_BC _WIDTH | <10:8>RW | The number of sysClk cycles that the PYXIS will wait before performing any Bcache transactions. |
| Reserved | <7:6>RO | N/A |
| CAS_LATENCY | <5:4>RW | This field defines the CAS latency of the SDRAMS used in the system. This field must be programmed to 2 or 3. If a 1 or 0 is programmed, it will be converted to 3 or 2, respectively. This field is initialized to 3. |
| Reserved | <3>RO | N/A |
| MIN_RAS_ PRECHARGE | <2:0>RW | The minimum precharge width for the RAMs when switched from one row to another. |