PYXIS Flash Control Register (FLASH_CTRL)
Address: 87.4000.0200
The flash control register controls that access to the flashROM and the basic timing associated with it. The register controls the write pulse width, the read/write access time, and the ability of the flash ROM to map at address 0 for startup conditions.
Reserved<31:14>N/A
FLASH_HIGH
_ENABLE		<13>RW When set to a 1, address range F.FC00.0000 through F.FFFF.FFFF. This code is in cacheable memory space and can contain program code. If all of the address bits are not connected, then the ROM may be shadowed at each ROM increment. Note: This is not the address space for programming the device.
FLASH_LOW
_ENABLE		<12>RW When set to 1, the flash ROM is mapped at address 0. This enables the device to be used in place of a serial ROM, which would normally contain the system initialization and startup. Initialize to 1 on power-up so that data can be executed from the flashROM. This should be disabled as soon after power-up as possible.
FLASH_ACCESS
_TIME		<11:8>RW The flash access time is determined by the cycle time of the system. The calculation is: Flash access time = (1 + (FLASH_ACCESS_TIME)) * cycle time - (Tpd+Tsetup). The Tpd is the PYXIS address bus clock-to-out delay, and the Tsetup is the PYXIS address bus setup time. If cycle time is 15ns and the value in FLASH_ACCESS_TIME is 0x0E, then the flash access time would be (1+14)* 15ns - 5ns or 255ns. This is only an example. The default value is 0x0f.
FLASH_DISABLE
_TIME		<7:4>RW Controls the number of cycles after FLASH_ROM_OE is de-asserted before PYXIS de-asserts ABUS_REQUEST to allow the processor to use the bus.
Flash disable time = (1 + (FLASH_DISABLE_TIME)) * cycle time. If cycle time is 15ns and the value in FLASH_DISABLE is 0C16, then the flash disable time would be (1+12)* 15ns or 195ns. This is only an example. The default value is 0716; writes are enabled.
FLASH_WP
_WIDTH		<3:0>RW Flash write pulse width is determined by the cycle time of the system. The calculation is: Flash write pulse width (nominal) = (1 + (FLASH_WP_WIDTH)) * cycle time. If cycle time is 15ns and the value in FLASH_WP_WIDTH is 0x0C, then the flash write pulse width would be (1+12)* 15ns or 195ns. This is only an example. The default value is 0x0f; writes are enabled.