The primary use of this register is during power management. There is the possibility that cache may be large enough that it would make flushing the entire cache take longer than a single interval timer cycle. This register provides the power management code the means to break the cache flushing sequence down into manageable pieces.

The table below describes the actual mapping of the register. The table contains the base address for the particular bit position and is 32 KB in length. The CVM register will encompass cache sizes from 0 to 1 MB.

The register can be used for caches larger than 1 MB as each bit is aliased. The bit field then represents the offset within each 1 MB bank.