|
Address: 87.4000.0140 The PYXIS Control register 1 register is a collection of bits that do not fit into any particular category but needed to be put somewhere. The original placement was based on CIA features that were added in later revisions of the ASIC in support of EV56 implementations. | ||
| Reserved | <31:13> | N/A |
| LW_PAR_MODE | <12>RW | When set to a "1", PCA56 Longword parity mode is selected. |
| Reserved | <11:9> | N/A |
| PCI_LINK_EN | <8>RW | I/O write chaining enable. |
| Reserved | <7:5> | N/A |
| PCI_MWIN_EN | <4>RW | Monster window enable. When set, gives full access to main memory. The monster window can be access by DAC only with PCI address<40> set. Memory address <33:0> equals PCI address<<33:0> |
| Reserved | <3:1> | N/A |
| IOA_BEN | <0>RW | Byte support enable. When set to a 1, the address range, 88.0000.0000 through EB.FFFF.FFFF are enable to provide byte, word, longword and quadword PCI addressing. This is a newly architected requirement. When set to 0, byte and word operations are disabled and accessing the above-mentioned addresses results in an error or undefined results. |