PYXIS Control Register Bit Descriptions

Address: 87.4000.0100

Reserved

<31>

N/A

RM_USE_HISTORY

<30>RW

When set, causes any translation buffer miss to use the prefetch algorithm in RM_TYPE and any translation buffer hit uses the length of the preceding DMA as the prefetch length.

RM_TYPE

<29:28>RW

This field controls the prefetch algorithm used for PCI memory read multiple command.

**PCI Read Prefetch Algorithm**
Value	Description
0 0	No prefetch
0 1	Fetch two cache lines. The operation will not cross an 8-KB boundary.
1 0	Fetch four cache lines. The operation will not cross a 8-KB boundary.
1 1	Fetch eight cache lines. The operation will not cross a 8-KB boundary.

Reserved

<27>

N/A

RL_USE_HISTORY

<26>RW

When se, causes any translation buffer miss to use the prefetch algorithm in RL_TYPE and any translation buffer hit uses the length of the preceding DMA as the prefetch length.

RL_TYPE

<25:24>RW

This field controls the prefetch algorithm used for PCI memory read line command. See the PCI Read Prefetch Algorithm table.

Reserved

<23>

N/A

RD_USE_HISTORY

<22>RW

When set, causes any translation buffer miss to use the prefetch algorithm in RD_TYPE and any translation buffer hit uses the length of the preceding DMA as the prefetch length.

RD_TYPE

<21:20>RW

This field controls the prefetch algorithm used for PCI memory read command. See the PCI Read Prefetch Algorithm table.

Reserved

<19:14>

N/A

ASSERT_IDLE_BC

<13>RW

0 - PYXIS will not assert IDLE BC pin while waiting for PCI read data.

1 - PYXIS will assert IDLE_BC pin while waiting for PCI read data.

ECC_CHK_EN

<12>RW

0 - PYXIS will not check IOD Data.

1 - PYXIS will check the IOD Data.

MCHK_ERR_EN

<11>RW

0 - PYXIS will not assert the ERROR Pin.

1 - PYXIS will assert the ERROR pin to report system machine check conditions.

FILL_ERR_EN

<10>RW

0 - PYXIS will not assert FILL_ERROR.

l - PYXIS will assert FILL_ERROR, if an error occurs during a EV56 read miss.

PERR_EN

<9>RW

0 - PYXIS will not check PCI data parity errors.

1 - PYXIS will check PCI data parity errors.

ADDR_PE_EN

<8>RW

0 - PYXIS will not check PCI address parity errors.

1 - PYXIS will check PCI address parity errors.

PCI_ACK64_EN

<7>RW

0 - PYXIS will not accept 64-bit PCI data transactions.

1 - PYXIS will accept 64-bit PCI data transactions.

PCI_REQ64_EN

<6>RW

0 - PYXIS will not request 64-bit PCI data transactions.

1 - PYXIS will request 64-bit PCI data transactions.

PCI_MEM_EN

<5>RW

0 - PYXIS will not respond to PCI transactions.

1 - PYXIS will respond to PCI transactions.

PCI_MST_EN

<4>RW

0 - PYXIS will not initiate PCI transactions.

1 - PYXIS will initiate PCI transactions.

FST_BB_EN

<3>RW

0 - PYXIS will not initiate fast back-to-back PCI transactions.

1 - PYXIS will initiate fast back to-back PCI transactions.

PCI_LOOP_EN

<2>RW

0 - PYXIS will not respond as a target when it is the master.

1 - PYXIS will respond as a target when it is the master.

Reserved

<1>

N/A

PCI_EN

<0>RW

0 - PYXIS asserts reset to the PCI
1 - PYXIS does not assert reset to the PCI.