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Address: 87.5000.0A00 - 87.5000.0BC0 The bank timing registers allow for the specific setup of the memory modules. The register allows mixing of memory DIMMs. | ||
| Reserved | <31:6>RO | N/A |
| SLOW_ PRECHARGE | <5>RW | When set, precharge operations are delayed for one cycle more than needed for the next CAS cycle. Some vendor SDRAMS (for example, NEC) require this when operating with a CAS latency of 3. |
| TOSHIBA | <4>RW | Toshiba SDRAMS do not permit a new CAS during several odd cycles after CAS. This bit is provided for these devices. It should be noted that the operation of this function is implemented by forcing auto-precharge. |
| Reserved _ENABLE | <3>RO | Enable subbanks. When set, subbanks are enabled and determined according to the BANK_SIZE table. When clear, subbanks are disabled, and the memRASB_I pins will be asserted only during refreshes. |
| ROW_ADDR _HOLD | <2:0>RW | The minimum number of sysClk cycles that RAS will be asserted before CAS is asserted. |