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Address: 87.5000.0800 - 87.5000.09C0 Each memory bank has a corresponding configuration register. This register contains mode bits and bits for memory address generation, as well as bank decoding. Banks 0 through 7 have the same limits on bank size and type of DRAMs used. The format of the configuration register is the same for baskets 0 through 7. Bank 8 is the VRAM bank. It supports different minimum DRAM sizes and configurations, therefore, its configuration register is different. With the exception of the valid bit, this register is not initialized. | ||||||||||||||||||||||||||||||||||||||||||||||
| Reserved | <31:8>RO | N/A | ||||||||||||||||||||||||||||||||||||||||||||
| 4BANK | <7>RW | When set, four bank operation is enabled for this bank. Typically 64-MB DIMMs. | ||||||||||||||||||||||||||||||||||||||||||||
| COLSEL | <6>RW | Row address selection. Indicates the number of valid Row bits expected at the DRAMs. Used along with memory width information to generate row or column addresses. There are two values associated with this field. A zero(0) indicates 12 bits of row address (16Mbit DRAM) and one(1) 14 bits of row address. (64Mbit DRAMs) | ||||||||||||||||||||||||||||||||||||||||||||
| SUBBANK _ENABLE | <5>RW | Enable subbanks. When set, subbanks are enabled and determined according to the BANK_SIZE table. When clear, subbanks are disabled, and the memRASB_I pins will be asserted only during refreshes. | ||||||||||||||||||||||||||||||||||||||||||||
| BANK_ SIZE<3:0> | <4:1>RW | Bank size in MB. Indicates the size of the bank in order to determine
which bits are used to compare the bank base address with the physical
address (PA) and to generate the subset. Corresponds to the total size of
the bank, including subbanks, if present.
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| BANK_ ENABLE | <0>RW | Bank Enabled. If set, all timing and configuration parameters for bank are valid, and access to banks allowed. If cleared, access to bank is not allowed. | ||||||||||||||||||||||||||||||||||||||||||||