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Address: 87.5000.0600 - 87.5000.07C0 Each memory bank has a corresponding base address register. The bits in this register are compared with the incoming sysAdr to determine the bank being addressed. The contents of this register are validated by setting the valid bit in the configuration register of that bank. The base address of each bank must begin on a naturally aligned boundary. (So, for a bank with 2 to the n addresses, the n least significant bits must be zero.) | ||
| Reserved | <31:16>RO | N/A |
| BASEADDR <33:24> | <15:6>RW | Starting memory address for the bank. |
| Reserved | <5:0>RO | N/A |