| Address: IPR CBU, FF.FFF0.0168 The EI_STAT register is a read-only register. Fill data from Bcache or main memory could have correctable or uncorrectable errors. System address/command parity errors are treated as uncorrectable hard errors. The register is locked on the first uncorrectable error. The register bits are locked until the EI_STAT register is read. | ||
| SEO_HRD_ERR | <35>R | Set when an errors occurs while one of the error bits in this register is set already. |
| FIL_IRD | <34>R | When set, this bit indicates that the error occurred during an I-ref fill. When clear, the error occurred during a D-ref fill. This bit is meaningful only when an ECC error bit is set. |
| EI_PAR_ERR | <33>R | When set, an address/command received by the CPU had a parity error. |
| UNC_ECC_ERR | <32>R | When set, fill data received from outside the CPU contained an uncorrectable ECC error. |
| COR_ECC_ERR | <31>R | When set, fill data received from outside the CPU contained a correctable ECC error. |
| EI_ES | <30>R | When set, this bit indicates that the error source is fill data from main memory or a system address/command parity error. When clear, the error source is fill data from the Bcache. This bit is meaningful only when COR_ECC_ERR, UNC_ECC_ERR, or EI_PAR_ERR is set. |
| BC_TC_PERR | <29>R | Indicates that a Bcache read transaction encountered bad parity in the tag control RAM. |
| BC_TPERR | <28>R | Indicates that a Bcache read transaction encountered bad parity in the tag address RAM. |
| CHIP_ID<3:0> | <27:24>R | Chip revision (currently, "4"). |