Dcache Parity Error Status Register (DC_PERR_STAT)

Address: IPR Mbox, Index=212 The Dcache parity error status (DC_PERR_STAT) register is a read/write register. If a Dcache parity error occurs while the DC_PERR_STAT is unlocked, the error status is loaded into <05:02>. The lock bit is set and the register is locked against further updates (except for the SEO bit) until software writes a 1 to clear the lock bit.
TP1	<05>R	This bit indicates a tag parity error in Dcache bank 1.
TP0	<04>R	This bit indicates a tag parity error in Dcache bank 0.
DP1	<03>R	This bit indicates a data parity error in Dcache bank 1.
DP0	<02>R	This bit indicates a data parity error in Dcache bank 0.
LOCK	<01>RW	This bit is set if a parity error occurred in the Dcache. Bits <05:02> are locked against further updates when this bit is set.
SEO	<00>RW	Second error occurred. Set when an error that normally locks the DC_STAT register occurs while the DC_STAT register is locked.