Memory ECC Syndromes and Addressing

When PYXIS detects a correctable ECC error, the ECC syndrome for the high quadword is latched on error into the ERROR_SYNDROME1 field in PYXIS_SYN<15:8>; the ECC syndrome for the low quadword is saved in the ERROR_SYNDROME0 field in PYXIS_SYN<7:0>.

When the CPU detects a correctable ECC error, the ECC syndrome for the high quadword is latched on error into FILL_SYN<15:8>. The ECC syndrome for the low quadword is saved in FILL_SYN<7:0>.

See the tables below for decoding single bit errors in the data and check bits. A syndrome of zero implies no error in that quadword. If the syndrome is not in the table, then the error involved more than one bit. Data bit numbers shown are in the low quadword; for errors in the high quadword, add 64 to the data bit number.

List of ECC syndrome codes sorted by syndrome.

List of ECC syndrome codes sorted by data bit.

When PYXIS detects a memory error, the memory address is latched into the MEAR and MESR registers. MEAR<31:4> contains ERROR_ADDR<31:4>; MESR<1:0> contains ERROR_ADDR<33:32>.

The physical DIMM associated with this address can be identified by inspecting the BBARx and BCRx registers (where "x" is the memory bank number zero through two).