ISA IRQ Assignments - The timer, keyboard, and mouse are hardwired to IRQs 0, 1, and 12, respectively.

The COM1 and COM2 ports are attached to IRQs 4 and 3, respectively.

The parallel port (LPT1) is assigned to IRQ7 by the AlphaBIOS firmware, although the Windows NT parallel port driver does not use interrupts. The driver uses programmed I/O by monitoring ready/busy. This means IRQ7 is available to other devices.

IRQ8, normally the interval timer interrupt, is not connected in the Personal Workstation a-Series. Instead, the timer interrupt signal RTC_INT is routed to the shift register. IRQ13, normally used to signal a co-processor error or signal the end of a DMA scatter/gather operation, is not connected in the system.

The primary IDE controller is assigned to IRQ14 and the secondary controller to IRQ15.

Care should be taken to avoid the sharing of ISA interrupts whenever possible. Check the operating system documentation and release notes to ensure interrupt sharing is supported by a particular operating system and device driver.

Interrupt Controller. The interrupt controller is the functional equivalent of two 82C59 controllers and is located in the PCI to ISA bridge chip. IRQ2 on the master controller is used to cascade the controllers together. This means that IRQ8-IRQ15 have a higher priority than IRQ3-IRQ7.
Shift Register. The PCI interrupts are not assigned to the typical IRQ system (ISA IRQs). Instead, the Personal Workstation a- Series uses a dedicated interrupt controller. The shift register is the input for the interrupt controller. The following interrupt signals are attached to the shift register:
Slot 3 <INTD:INTA>
Bits 31:28. Each PCI slot has four interrupt signals available (INTA, INTB, INTC, and INTD). Typically, PCI devices use INTA. PCI boards with multiple devices may use more than one INT signal. The interrupts from individual lines are all directed to CPU interrupt line IRQ_H<1>. The INT_MASK register can be used to mask off various interrupt signals.
Slot 2 <INTD:INTA>
Bits 27:24 - Each PCI slot has four interrupt signals available (INTA, INTB, INTC, and INTD). Typically, PCI devices use INTA. PCI boards with multiple devices may use more than one INT signal.
Slot 1 <INTD:INTA>
Bits 23:20 - Each PCI slot has four interrupt signals available (INTA, INTB, INTC, and INTD). Typically, PCI devices use INTA. PCI boards with multiple devices may use more than one INT signal.
Slot 5 <INTD:INTA>
Bits 19:16 - Each PCI slot has four interrupt signals available (INTA, INTB, INTC, and INTD). Typically, PCI devices use INTA. PCI boards with multiple devices may use more than one INT signal.
Slot 4 <INTD:INTA>
Bits 15:12 - Each PCI slot has four interrupt signals available (INTA, INTB, INTC, and INTD). Typically, PCI devices use INTA. PCI boards with multiple devices may use more than one INT signal.
Bit 11, Reserved for USB.
Bit 10, Reserved.
Bit 9, IDE. The IDE PCI interrupt is not used. The IDE controller is used in "IDE legacy" mode. Therefore, it uses ISA IRQ14 and 15.
Bit 8, Ethernet. When its interrupt is enabled, the Ethernet controller on the riser card has its interrupt sent to the CPU over IRQ_H<1>.
Bit 7, PCI/ISA Bridge. The INT signal from the PCI/ISA bridge is used signal interrupts from the ISA IRQ system. The interrupt is routed to the CPU on IRQ_H<1>.
Bit 6, RTC. The realtime clock in the SuperI/O chip can be programmed to generate a periodic interrupt. It is routed to the CPU on IRQ_H<2>.
Bits 5:4 (CID1:CID0). These two signals are used during POST to identify the type of riser card installed.
Bit 3, Reserved.
Bit 2, Switch. The switch position is sensed during POST. AlphaBIOS will clear the firmware passwords if the switch is held during power on and POST. Pressing the switch results in IRQ_H<1> being sent to the CPU.
Bit 1, NMI. The nonmaskable interrupt signal comes from the PCI/ISA bridge chip. NMI indicates that a SERR (PCI system error condition) or IOCHK (parity or other uncorrectable on the ISA bus) occurred. NMI results in a machine check interrupt (SYS_MCH_CHK_IRQ_H).
Bit 0, Fan Fault. Set if an overcurrent condition occurs in either fan. A fan fault results in a machine check interrupt (SYS_MCH_CHK_IRQ_H).
Core Logic. The core logic clocks in the contents of the shift register into the interrupt request register (INT_REQ). Several internal registers are used to control interrupt routing (INT_ROUTE), enabling (INT_MASK), and polarity of the input signal (INT_HILO). Interrupts that get through the core logic are sent to the CPU over one of seven interrupt lines.
CPU Interrupts. Seven lines are used to signal interrupts to the CPU. During initialization, these signals are used to set up the CPU cycle time divisor.
sys_mch_chk_irq_h - NMI and fan fault (IPL 31). The system machine check interrupt is used to indicate catastrophic errors.
irq_h<0> - Not used? (IPL 20)
irq_h<1> - PCI and ISA devices (IPL21). PCI device interrupts and 8259-compatible types (ISA device interrupts).
irq_h<2> - TOY clock (IPL 22). The TOY chip provides a periodic interrupt.
irq_h<3> - Reserved (IPL 23)
mch_hlt_irq_h - Not used. Machine halt interrupt request. There is no provision for halting the Personal Workstation a-Series systems.
pwr_fail_irq_h - Reserved (IPL 30): Power fail interrupt request (not used).