PCI IDSEL Assignments
Topics covered in this section include:
PCI IDSEL Assignments |
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The PCI bus must be initialized each time the system is powered on. Configuration cycles (accesses to CPU addresses 87.0000.0000 through 87.1fff.ffff) are used for this purpose. The initialization device select (IDSEL) input selects a PCI device during configuration read and write transactions. The AD bits associated with the PCI devices in the Personal Workstation a-Series are shown below:
|
Device |
IDSEL Bit |
PCI Base |
CPU Base |
| Ethernet Controller | AD[14] | 0000.4000 | 87.0003.0000 |
| IDE | AD[15] | 0000.8000 | 87.0004.0000 |
| USB (if present) | AD[17] | 0002.0000 | 87.0006.0000 |
| PCI/ISA Bridge | AD[18] | 0004.0000 | 87.0007.0000 |
| PCI/PCI Bridge | AD[19] | 0008.0000 | 87.0000.0000 |
| PCI Slot 4 | AD[22] | 0040.0000 | 87.000B.0000 |
| PCI Slot 5 | AD[23] | 0080.0000 | 87.000C.0000 |
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| PCI Slot 1 | AD[24] | 0100.0000 | 87.000D.0000 |
| PCI Slot 2 | AD[25] | 0200.0000 | 87.000E.0000 |
| PCI Slot 3 | AD[26] | 0400.0000 | 87.000F.0000 |
CPU base address [20:16] represents the encoded value of the IDSEL bit to be asserted (IDSEL bits range from PCI AD[31:11). For example, in a CPU base address of 87.0006.0000, the encoded IDSEL value is 06. Starting at PCI AD[11] and counting up 7 bits (0-6) points to PCI AD[17], which is hardwired as an IDSEL line to the Ethernet controller.
PCI Address Space and Configuration Tasks |
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The PCI specification defines three physical address spaces. Besides the usual memory and I/O space, there is a configuration address space. Configuration address space allows the devices to be initialized and configured by software/firmware. PCI devices have 256 bytes of configuration register information. Of the 256 bytes, 64 bytes are the predefined header region. The remaining 192 bytes are device-specific.
The console firmware performs the following PCI-configuration tasks:
| Task | Action |
|---|---|
| Determine what PCI devices are present. | Try to read the ID registers. |
| When a device is located, determine its address space requirements. | All 1's are written to its base address register. Device returns the address bits it uses set to 1's; all others are 0's. |
| Initialize the base registers. | Set up all base address registers in order from largest to smallest. |
PCI Predefined Header Region |
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31 16 15 0 +--------------------------+--------------------------+ | Device ID | Vendor ID | 00h +--------------------------+--------------------------+ | Status | Command | 04h +--------------------------+-----------+--------------+ | Class Code | Revision ID | 08h +-----------+--------------+-----------+--------------+ | BIST | Header Type |Latency Tmr| Cache Ln Size| 0Ch +-----------+--------------+-----------+--------------+ | Base Address Registers | 10h- | | 24h +--------------------------+--------------------------+ | Reserved | 28h- | | 2C +--------------------------+--------------------------+ | Expansion ROM Base Address | 30h +--------------------------+--------------------------+ | Reserved | 34h- | | 38h +------------+-------------+------------+-------------+ | Max_lat | Min_gnt | Intr Pin | Intr Line | 3Ch +------------+-------------+------------+-------------+
PCI Arbitration |
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Arbitration for the PCI bus is handled by a PAL chip and the PCI/ISA bridge chip.
+---------+
CPU REQ ----| |-- CPU GNT
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PCI slot 4 REQ -----------------| PCI/ISA |-- Slot 4 GNT
PCI slot 5 REQ -----------------| |-- Slot 5 GNT
PCI-to-PCI Bridge REQ ----------| Bridge |-- PCI-to-PCI GNT
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+-------+ REQ3 | |
| |-------------| |---+-- GNT3
ENET REQ -| | | | |
IDE REQ --| PAL | | | |
| | +---------+ |
| |--- ENET GNT |
GNT3 -+---| |--- IDE GNT |
| | | |
| +-------+ |
+---------------------------------------+
ISA Bus |
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The DIGITAL Personal Workstation a-Series has two built-in ISA devices as well as slots for up to three additional ISA options (if the slots are not already occupied by PCI devices). The built-in devices are: