CPU - The CPU is a Digital Semiconductor 21164 with the following features: Superscalar pipelined processor manufactured using 0.35-micrometer CMOS technology. Quad-instruction issue. Two on-chip high-throughput floating point units (FPUs) capable of executing both Digital and IEEE floating-point data types. Instruction cache: 8 KB on-chip, virtual, direct-mapped cache with 32-byte blocks. Data cache: Dual-read-ported 8 KB on-chip write-through, direct-mapped, read allocated, physical cache with 32-byte blocks. Second-level cache: 96 KB, three-way, set-associative, physical, writeback, write allocate, mixed instruction, and data cache, with 32- or 64-byte blocks. Write buffer with six 32-byte entries. Demand-paged memory management unit with a 48-entry I-stream translation buffer and a 64-entry D-stream translation buffer. Parity for the on-board Icache, Dcache, and Scache memories and the data bus. Uses 3.3V for external and 2.0V for internal.

Index Bus - The index bus uses index [25:04] from the CPU to address the Bcache and the tag and state bits for determining hits and conherence. The tag data field bits are [38:20] and data parity. State bits are valid, dirty, and control parity.

Bcache - Bcache is available as either a 2-MB or 4-MB option. The Bcache uses synchronous SRAMs and has a 15-ns access time.

Inter-IC (I2C) Serial Bus - The I2C bus collects information about the various optional components of the system. The Pyxis chip operates as the bus master, with slave devices on each of the six DIMMs, the riser card, and the Bcache module.

CPU Data Bus - The CPU data bus connects the CPU, Bcache, and switch. CPU data bus width: 128 bits plus 16 ECC bits.

Switch - The switch isolates the CPU/Bcache from the core logic/main memory.

System Address Bus - The system address bus connects the CPU address [39:4] to the core logic. Also, the flashROM is located on the system address bus.

FlashROM - The 1-MB flashROM contains the equivalent SROM code (system has no SROM), two copies of nonvolatile environment variables, diagnostic code, AlphaBIOS firmware, and SRM firmware. Core logic controls flashROM access. The flashROM is attached to the system address bus. The address busses [11:4] are used to send ROM read data from the flashROM to the core logic during system initialization. Address bits [31:12] address the flashROM.

Memory Bus - The memory bus connects the switch and the core logic to the main memory DIMMs. Width to/from memory: 128 data bits plus 16 ECC bits.

Memory - The main memory system has the following features: Unbuffered 3.3V SDRAM chips mounted on 168-pin dual inline memory modules (DIMMs) Six DIMM sockets on the MLB arranged in three banks: 0, 1, and 2. The two DIMMs in a bank must be identical.) Total size ranges from 32 MB to 1.5 GB (when 256-MB DIMMs are available). Each bank (two DIMMs) is 128-bits data plus 16-bits ECC wide.

Core Logic - Core logic is implemented on a single 474-pin BGA chip and provides the following functions: Synchronous DRAM memory controller providing the row and column address and the memory control signals (CAS and RAS) for the memory banks. 33-MHz 64-bit PCI interface. Startup from flashROM. 96-ns memory latency (with 100-MHz DRAMs). 1333 Mbps peak memory bandwidth. Up to 64 interrupts through an external shift register. Up to 32 general purpose inputs and outputs through external shift registers. 3.3V design.

Memory Address Bus - Core logic addresses the main memory using DRAM address [13:0].

PCI Bus (Primary) - The primary peripheral component interconnect (PCI) bus is a 64-bit-wide multiplexed address/data bus with a clock speed of 33.33 MHz. PCI bus provides the system with its primary I/O interconnect. Core logic acts as the PCI host. Two 64-bit PCI expansion slots, a 10/100 Mbps Ethernet controller and a PCI/PCI bridge are attached to the primary PCI bus. PCI bus width: 64 bits (AD[63:0]). An even parity bit (PAR) is calculated on 36 bits ( AD[31:0] and C/BE[3:0]. Another even parity bit (PAR64) is calculated on the upper 36 bits {AD[63:32] and C/BE[7:4]).

IDE Controller - The integrated drive electronics (IDE) controller is a CMD PCI0646 chip. The controller provides two 16-bit channels (primary and secondary). Interface can support up to two devices (master and slave) on each channel. Interface runs in IDE legacy mode versus PCI native mode. This allows use of both channels but restricts the system from using any other legacy IDE chips. The chip supports data rates up to 16.6 Mbps peak using PIO modes one through four and DMA modes one and two.

PCI/ISA Bridge - The PCI/ISA bridge manages traffic flow between the primary PCI bus and the ISA bus. The bridge is an Intel 82378ZB System I/O chip. Three ISA expansion slots, the audio subsystem, and the super I/O chip (floppy, COM1, COM2, KB, Mouse, RTC, and parallel port) are attached to the ISA bridge.

ISA Bus - The ISA bus originates at the PCI-ISA bridge. In addition to the three ISA slots on the riser card, the ISA bus connects to the Super I/O chip (adapter for the floppy disk, two serial lines, keyboard, mouse, realtime clock, and parallel port) and the audio controller. The ISA bus data width is 16 bits.

SuperI/O - The Super I/O chip (National PC87303) is attached to the ISA bus and has the following functions: Floppy disk controller (FDC) Two serial lines (UARTs) (COM1 and COM2) Enhanced bidirectional parallel port Mouse and keyboard Realtime clock

Ethernet - The 10/100 Mb/s Ethernet LAN controller (DC21142) is embedded in the system on the riser card. It is attached to the primary PCI bus. External access is provided through either one of the following cards mounted to the rear of the enclosure: Media adapter unit (MAU) for Twisted-Pair(10BaseT) and ThinWire (10Base2) for 10 Mbps operation. Media-independent interface (MII) card with a twisted-pair connector for use with a 100 Mbps fast Ethernet interface.

Audio - An ESS Technology ES1888 AudioDrive(R) chip, located on the riser card, brings 16-bit stereo audio and 20-voice FM music synthesis to the system. The chip can record, compress, and play back voice, sound, and music with built-in seven-channel-mixer controls. It supports full duplex operation for simultaneous record and playback using two DMA channels. Microphone and headphone connectors are located on the upper-left side near the system front. A small card provides rear-accessible connectors for line in, speaker out, and MIDI/game port.

PCI/PCI Bridge - The PCI-to-PCI bus bridge (DC21052) is located on the riser card. The bridge allows the use of three additional 32-bit PCI slots (electrical loading considerations preclude putting those slots on the primary PCI bus).

PCI Bus (Secondary) - The secondary peripheral component interconnect (PCI) bus is a 32-bit-wide multiplexed address/data bus with a clock speed of 33.33 MHz. The PCI bus provides the system with a connection to the three 32-bit PCI expansion slots through the PCI/PCI bridge.

Expansion Slots - The riser card contains five expansion slots with the following capabilities: Slot 1: PCI only, 32-bit PCI (secondary bus), half-size cards only. Slot 2: PCI/ISA combination, 32-bit PCI (secondary bus), half-size cards only. Slot 3: PCI/ISA combination, 32-bit PCI (secondary bus), full-size cards. Slot 4: PCI/ISA combination, 32- or 64-bit PCI (primary bus), full-size cards. Slot 5: PCI only, 32- or 64-bit PCI (primary bus), full-size cards.